US4916520A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with airbridge interconnection
Assignee: NEC Corp
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Filing: 1988-09-13
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Granted: 1990-04-10
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Expires: 2008-09-13
Abstract
Abstract There is disclosed a semiconductor device comprising a plurality of lower level interconnections having first, second and third lower level interconnections, an upper level interconnection connected to the first and second lower level interconnections and extending over the third lower level interconnection in spacing relationship, and at least one pier formed on a central portion of the upper surface of one of the first and second lower level interconnections, and the pier has a width less than that of aforesaid one of the first and second lower level interconnections and is covered in its entire surface with a film formed of the same material as of the upper level interconnection, so that a force applied for wafer separation is partially supported by the pier.
Inventors
- 👤 Yasumi Kurashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/432
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
159 words
A semiconductor device fabricated on a semiconductor substrate overlain by a first insulating film, comprising: (a) a plurality of lower level interconnections formed on said first insulating film, said lower level interconnections having first, second and third lower level interconnections, said first and second lower level interconnections being located on both sides of said third lower level interconnection; (b) an upper level interconnection connected to said first and second lower level interconnections and extending over said third lower level interconnection, said upper level interconnection being spaced from said third lower level interconnection; and (c) at least one pier formed on a central portion of an upper surface of one of said first and second lower level interconnections, said pier having a width less than that of the aforesaid one of the first and second lower level interconnections and being covered over its entire exposed surface with a film formed of the same material as of said upper level interconnection.
Claim 2
Dependent Claim
159 words
A semiconductor device fabricated on a semiconductor substrate overlain by a first insulating film, comprising: (a) a plurality of lower level interconnections formed on said first insulating film, said lower level interconnections having first, second and third lower level interconnections, said first and second lower level interconnections being located on both sides of said third lower level interconnection; (b) an upper level interconnection connected to said first and second lower level interconnections and extending over said third lower level interconnection, said upper level interconnection being spaced from said third lower level interconnection; and (c) at least one pier formed on a central portion of an upper surface of one of said first and second lower level interconnections, said pier having a width less than that of the aforesaid one of the first and second lower level interconnections and being covered over its entire exposed surface with a film formed of the same material as of said upper level interconnection.
Claim 3
Dependent Claim
42 words
A semiconductor device as set forth in claim 1, in which a portion of said upper level interconnection over said third lower level interconnection is approximately equal in height to a portion of said film covering an upper surface of said pier.
Claim 4
Dependent Claim
31 words
A semiconductor device as set forth in claim 2, in which at least one of said lower level interconnections serves as a bonding pad which is kept idle in electrical operations.
Claim 5
Dependent Claim
87 words
A semiconductor device as set forth in claim 3, in which another pier is further formed on said bonding pad and has a width less than that of the aforesaid one of said first and second lower level interconnections so that the entire surface of said another pier is covered with a conductive strip, the portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said conductive strip covering an upper surface of said another pier.
Claim 6
Dependent Claim
17 words
A semiconductor device as set forth in claim 4, in which each pier is formed of polymide.
Claim 7
Dependent Claim
350 words
A semiconductor device fabricated on a semiconductor substrate overlain by a first insulating film, comprising: (a) a plurality of lower level interconnections formed on said first insulating film, said lower level interconnections having first, second and third lower level interconnections, said first and second lower level interconnections being located on both sides of said third lower level interconnection; (b) an upper level interconnection connected to said first and second lower level interconnections and extending over said third lower level interconnection, said upper level interconnection being spaced from said third lower level interconnection; and (c) at least one pier formed on a central portion of an upper surface of one of said first and second lower level interconnections, said pier having a width less than that of the aforesaid one of the first and second lower level interconnections and being covered over its entire exposed surface with a film formed of the same material as of said upper level interconnection, a portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said film covering an upper surface of said pier, at least one of said lower level interconnections serving as a bonding pad which is kept idle in electrical operations, another pier being further formed on said bonding pad and having a width less than that of the aforesaid one of said first and second lower level interconnections so that the entire surface of said another pier is covered with a conductive strip, the portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said conductive strip covering an upper surface of said another pier, said semiconductor device being further provided with first and second pillow strips buried under aforesaid one of said first and second lower level interconnections and said bonding pad, respectively, the portion of said upper level interconnection over said third lower level interconnection being lower than the portion of said film covering the upper surface of said pier and the portion of said conductive strip.
Claim 8
Dependent Claim
350 words
A semiconductor device fabricated on a semiconductor substrate overlain by a first insulating film, comprising: (a) a plurality of lower level interconnections formed on said first insulating film, said lower level interconnections having first, second and third lower level interconnections, said first and second lower level interconnections being located on both sides of said third lower level interconnection; (b) an upper level interconnection connected to said first and second lower level interconnections and extending over said third lower level interconnection, said upper level interconnection being spaced from said third lower level interconnection; and (c) at least one pier formed on a central portion of an upper surface of one of said first and second lower level interconnections, said pier having a width less than that of the aforesaid one of the first and second lower level interconnections and being covered over its entire exposed surface with a film formed of the same material as of said upper level interconnection, a portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said film covering an upper surface of said pier, at least one of said lower level interconnections serving as a bonding pad which is kept idle in electrical operations, another pier being further formed on said bonding pad and having a width less than that of the aforesaid one of said first and second lower level interconnections so that the entire surface of said another pier is covered with a conductive strip, the portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said conductive strip covering an upper surface of said another pier, said semiconductor device being further provided with first and second pillow strips buried under aforesaid one of said first and second lower level interconnections and said bonding pad, respectively, the portion of said upper level interconnection over said third lower level interconnection being lower than the portion of said film covering the upper surface of said pier and the portion of said conductive strip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |