US4308090A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: US Philips Corp
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Filing: 1979-03-02
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Granted: 1981-12-29
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Expires: 1999-03-02
Abstract
Abstract A method of manufacturing a semiconductor device having a multi-layer wiring system includes the steps of providing a first pattern of conductive regions on a major surface, providing an intermediate conductive layer over the major surface and the first pattern conductive regions, providing a second pattern of conductive tracks on the intermediate layer, and selectively etching the intermediate layer using the second pattern of tracks as an etching mask to completely remove the intermediate layer by underetching below portions of the second pattern tracks crossing over portions of the first pattern of conductive region where no electrical interconnection between the first and second conductive patterns is desired, while only partially removing the intermediate layer by underetching below portions of the second pattern of tracks crossing over portion of the first pattern of semiconductor regions where an electrical interconnection between the first and second conductor patterns is desired. In this manner, at least two separate parts of the first pattern of conductive regions are conductively connected at selected locations by a part of the second pattern of tracks in a method in which the conductive tracks of the uppermost level are used at a self-aligning etching mask.
Inventors
- 👤 Ties S. Te Velde
- 👤 Donald R. Wolters
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:42
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/483
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
353 words
A method of manufacturing a semiconductor device comprising a semiconductor body having a first pattern of conductive regions on a major surface thereof and a second pattern of conductive tracks crossing over but spaced apart from said first regions and electrically connected thereto only at selected locations, which comprises: providing a semiconductor body having a major surface; providing a first pattern of conductive regions on said major surface; providing an intermediate conductive layer over the major surface of the body and first pattern, which intermediate layer is capable of being selectively etched with respect to the material of the second pattern of tracks and which can adhere well to the material of the first pattern of regions and the second pattern of tracks; providing the second pattern of conductive tracks on the intermediate layer; selectively etching the intermediate layer using the second pattern of tracks as an etching mask to completely remove the intermediate layer by underetching at least below a first portion of the second pattern of tracks crossing over a portion of the first pattern of conductive regions where no electrical interconnection between the first and second conductive patterns is desired, to only partially remove the intermediate layer by underetching below a second portion of the second pattern of tracks crossing over a portion of the first pattern of conductive regions where an electrical interconnection between the first and second conductive patterns is desired, and to only partially remove the intermediate layer by underetching below a third portion of the second pattern of tracks not crossing over a portion of the first pattern of conductive regions so that the remaining part of the intermediate layer on said major surface and beneath said third portion of the second pattern of tracks forms a pier to support said third portion, at least two separate parts of the first pattern of conductive regions being conductively connected at selected locations by at least a part of the second pattern of tracks, said part of the second pattern being supported at said third portion intermediate said two separate parts of the first pattern by said pier.
Claim 2
Independent Claim
353 words
A method of manufacturing a semiconductor device comprising a semiconductor body having a first pattern of conductive regions on a major surface thereof and a second pattern of conductive tracks crossing over but spaced apart from said first regions and electrically connected thereto only at selected locations, which comprises: providing a semiconductor body having a major surface; providing a first pattern of conductive regions on said major surface; providing an intermediate conductive layer over the major surface of the body and first pattern, which intermediate layer is capable of being selectively etched with respect to the material of the second pattern of tracks and which can adhere well to the material of the first pattern of regions and the second pattern of tracks; providing the second pattern of conductive tracks on the intermediate layer; selectively etching the intermediate layer using the second pattern of tracks as an etching mask to completely remove the intermediate layer by underetching at least below a first portion of the second pattern of tracks crossing over a portion of the first pattern of conductive regions where no electrical interconnection between the first and second conductive patterns is desired, to only partially remove the intermediate layer by underetching below a second portion of the second pattern of tracks crossing over a portion of the first pattern of conductive regions where an electrical interconnection between the first and second conductive patterns is desired, and to only partially remove the intermediate layer by underetching below a third portion of the second pattern of tracks not crossing over a portion of the first pattern of conductive regions so that the remaining part of the intermediate layer on said major surface and beneath said third portion of the second pattern of tracks forms a pier to support said third portion, at least two separate parts of the first pattern of conductive regions being conductively connected at selected locations by at least a part of the second pattern of tracks, said part of the second pattern being supported at said third portion intermediate said two separate parts of the first pattern by said pier.
Claim 3
Dependent Claim
30 words
A method as claimed in claim 1, wherein the conductive tracks of the second pattern are wider at the second and third portions thereof than at the first portion thereof.
Claim 4
Dependent Claim
39 words
A method as claimed in claim 2, wherein the width of the conductive tracks of the second pattern at the second and third portions thereof is at least twice the width of said tracks at the first portion thereof.
Claim 5
Dependent Claim
14 words
A method as claimed in claim 1, wherein the intermediate conductive layer comprises nickel.
Claim 6
Dependent Claim
17 words
A method as claimed in claim 4, wherein at least one of the conductive patterns comprises aluminum.
Claim 7
Dependent Claim
43 words
A method as claimed in claim 5, wherein at least one of the conductive patterns comprises a double layer having a first layer portion comprising gold and a second layer portion comprising a metal selected from the group consisting of platinum and titanium.
Claim 8
Dependent Claim
36 words
A method as claimed in claim 1, wherein the conductive tracks of the second pattern are provided with apertures at first region crossover points where the second pattern and first region are not to be connected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-28 | 1985-06-29 | 1985-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-28 | 1989-06-29 | 1989-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-28 | 1993-06-29 | 1993-12-29 | $7700.00 | Window Closed / Lapsed |