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US4912734A
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High resolution event occurrance time counter
Assignee: AIL Systems Inc
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Filing: 1989-02-14
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Granted: 1990-03-27
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Expires: 2009-02-14
Abstract
Abstract A high resolution event occurrence time counter includes a free running counter which is responsive to a clock signal and which provides count data that varies in response to the clock signal. A first register stores the count data of the free running counter. The first register provides first register data representative of the count data stored in the register. A second register stores the first register data and provides first time of arrival data representative of the first register data stored in the second register. A third register stores the count data of the free running counter. The third register provides second time of arrival data representative of the count data which is stored in the third register. A clock edge encoder determines whether an event occurred during the first half cycle of the clock signal or during the second half cycle. The clock edge encoder provides a first sync signal when the event occurred during the first half cycle, and a second sync signal when the event occurred during the second half cycle. The second register stores the first register data in response to the first sync signal, and the third register stores the count data in response to the second sync signal. Either the first time of arrival data or the second time of arrival data, depending on whether the first or second sync signal is generated, is provided as output time of arrival data of the event occurrence time counter.
Inventors
- 👤 Richard M. Frauenglass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:41
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/04; H; H03; H03K; H03K21/00; H03K21/40; H03K23/00; H03K23/40; H03K23/50; H03K23/54; H03K23/542
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
326 words
A high resolution event occurrence time counter, which comprises: free running counter means, the counter means being responsive to a clock signal and providing count data which varies in response to the clock signal, the clock signal being periodic, each period of the clock signal having a first half period and a second half period; first register means for storing the count data of the free running counter means, the first register means being responsive to the clock signal and storing the count data in response thereto, the first register means providing first register data representative of the count data stored therein; second register means for storing the first register data of the first register means, the second register means providing first time of arrival data representative of the first register data stored therein; third register means for storing the count data of the free running counter, the third register means providing second time of arrival data representative of the count data stored therein; clock edge encoder means for determining whether an event occurred during one of the first half period and the second half period of the clock signal, the clock edge encoder means providing a first sync signal when the event occurred during the first half period, and a second sync signal when the event occurred during the second half period; the second register means being responsive to the first sync signal and storing the first register data in response thereto; the third register means being responsive to the second sync signal and storing the count data in response thereto; wherein at least the first time of arrival data is provided as output data of the event occurrence time counter when at least the first sync signal is provided by the clock edge encoder means, and at least the second time of arrival data is provided as output data when at least the second sync signal is provided by the clock edge encoder means.
Claim 2
Dependent Claim
326 words
A high resolution event occurrence time counter, which comprises: free running counter means, the counter means being responsive to a clock signal and providing count data which varies in response to the clock signal, the clock signal being periodic, each period of the clock signal having a first half period and a second half period; first register means for storing the count data of the free running counter means, the first register means being responsive to the clock signal and storing the count data in response thereto, the first register means providing first register data representative of the count data stored therein; second register means for storing the first register data of the first register means, the second register means providing first time of arrival data representative of the first register data stored therein; third register means for storing the count data of the free running counter, the third register means providing second time of arrival data representative of the count data stored therein; clock edge encoder means for determining whether an event occurred during one of the first half period and the second half period of the clock signal, the clock edge encoder means providing a first sync signal when the event occurred during the first half period, and a second sync signal when the event occurred during the second half period; the second register means being responsive to the first sync signal and storing the first register data in response thereto; the third register means being responsive to the second sync signal and storing the count data in response thereto; wherein at least the first time of arrival data is provided as output data of the event occurrence time counter when at least the first sync signal is provided by the clock edge encoder means, and at least the second time of arrival data is provided as output data when at least the second sync signal is provided by the clock edge encoder means.
Claim 3
Dependent Claim
30 words
A high resolution event occurrence time counter as defined by claim 1, wherein the free running counter means includes a Johnson-type counter and a binary counter coupled together in series.
Claim 4
Dependent Claim
90 words
A high resolution event occurrence time counter as defined by claim 1, wherein the second register means are cleared of first register data in response to the second sync signal provided by the clock edge encoder means, and the third register means are cleared of count data in response to the first sync signal provided by the clock edge encoder means, whereby only one of the first time of arrival data and the second time of arrival data will be provided as output data of the event occurrence time counter.
Claim 5
Dependent Claim
52 words
A high resolution event occurrence time counter, as defined by claim 3, which further comprises OR means for logic or'ing together the first time of arrival data and the second time of arrival data, the OR means providing output data corresponding to one of the first and second time of arrival data.
Claim 6
Dependent Claim
68 words
A high resolution event occurrence time counter, as defined by claim 1, wherein the output data of the event occurrence time counter includes a least significant bit having a first logic state if at least the first sync signal is provided by the clock edge encoder means, and having a second logic state if at least the second sync signal is provided by the clock edge encoder means.
Claim 7
Dependent Claim
77 words
A high resolution event occurrence time counter, as defined by claim 1, wherein the clock edge encoder means further includes means for indicating when output data of the event occurrence time counter is available, the output data indicating means counting a predetermined number of periods of the clock signal after the event has occurred and providing a signal indicating that output data of the event occurrence time counter is available to be provided to an external circuit.
Claim 8
Dependent Claim
46 words
A high resolution event occurrence time counter, as defined by claim 1, wherein the counter means provides a carry signal, the carry signal being provided as an output of the event occurrence time counter so as to be available to be provided to an external counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |