Patent US4912054A successfully refreshed from Google Patents.
US4912054A
Expired / Lapsed
US
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Integrated bipolar-CMOS circuit isolation process for providing different backgate and substrate bias
Assignee: Texas Instruments Inc
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Filing: 1989-01-06
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Granted: 1990-03-27
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Expires: 2009-01-06
Abstract
Abstract Disclosed is a proces for making a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.
Inventors
- 👤 Stephen R. Tomassetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:03
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D84/00; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
115 words
A method for fabricating a bipolar-CMOS circuit, comprising the steps of: forming a bipolar transistor in a semiconductor substrate; forming a CMOS circuit comprising a PMOS transistor and an NMOS transistor in the substrate; electrically isolating the NMOS transistor from the substrate by forming a semiconductor isolation ring around said NMOS transistor; forming a connection to the substrate for connection thereof to a voltage source; and forming a different connection to the isolated NMOS transistor for providing a backgate bias to the NMOS transistor, said backgate bias being of a different magnitude than said voltage source, whereby the substrate can be biased with a voltage different than a voltage applied to the NMOS transistor backgate.
Claim 2
Independent Claim
115 words
A method for fabricating a bipolar-CMOS circuit, comprising the steps of: forming a bipolar transistor in a semiconductor substrate; forming a CMOS circuit comprising a PMOS transistor and an NMOS transistor in the substrate; electrically isolating the NMOS transistor from the substrate by forming a semiconductor isolation ring around said NMOS transistor; forming a connection to the substrate for connection thereof to a voltage source; and forming a different connection to the isolated NMOS transistor for providing a backgate bias to the NMOS transistor, said backgate bias being of a different magnitude than said voltage source, whereby the substrate can be biased with a voltage different than a voltage applied to the NMOS transistor backgate.
Claim 3
Dependent Claim
23 words
The method of claim 1 further including connecting the backgate of the NMOS transistor to a semiconductor source region of the NMOS transistor.
Claim 4
Dependent Claim
15 words
The method of claim 2 further including grounding the source region of the NMOS transistor.
Claim 5
Dependent Claim
29 words
The method of claim 1 further including connecting the backgate and a semiconductor source region of the NMOS transistor to ground, and connecting the substrate to a negative voltage.
Claim 6
Independent Claim
142 words
A method for fabricating a bipolar-CMOS semiconductor circuit, comprising the steps of: forming in the face of a semiconductor substrate plural semiconductor regions of a first and second conductivity type; forming a PMOS circuit in said semiconductor region of a first conductivity type; forming a plurality of doped buried layers underlying ones of said semiconductor regions; forming a doped semiconductor deep collector region in contact with one said buried layer; forming a bipolar transistor in a semiconductor region of a first conductivity type adjacent said deep collector; forming a doped isolation ring for isolating a portion of a semiconductor region of a second conductivity type, and forming said isolation ring in contact with one of said buried layers; and forming an NMOS device in said isolated semiconductor region, such that the bipolar transistor and said PMOS circuit are isolated from one another.
Claim 7
Independent Claim
142 words
A method for fabricating a bipolar-CMOS semiconductor circuit, comprising the steps of: forming in the face of a semiconductor substrate plural semiconductor regions of a first and second conductivity type; forming a PMOS circuit in said semiconductor region of a first conductivity type; forming a plurality of doped buried layers underlying ones of said semiconductor regions; forming a doped semiconductor deep collector region in contact with one said buried layer; forming a bipolar transistor in a semiconductor region of a first conductivity type adjacent said deep collector; forming a doped isolation ring for isolating a portion of a semiconductor region of a second conductivity type, and forming said isolation ring in contact with one of said buried layers; and forming an NMOS device in said isolated semiconductor region, such that the bipolar transistor and said PMOS circuit are isolated from one another.
Claim 8
Dependent Claim
54 words
The method of claim 5 further including forming a backgate electrical contact in said isolated semiconductor region, and forming a different contact in electrical contact with a semiconductor region circumscribing said isolation ring, whereby a bias can be applied to the isolated semiconductor region which is different than a bias applied to said substrate.
Claim 9
Dependent Claim
28 words
The method of claim 6 further including connecting said backgate to a potential which is less than a potential connected to said semiconductor region circumscribing said isolation ring.
Claim 10
Dependent Claim
22 words
The method of claim 5 wherein said deep collector is formed during the same steps utilized in forming said semiconductor isolation ring.
Claim 11
Dependent Claim
15 words
The method of claim 5 wherein said isolated semiconductor region comprises a P-type epitaxial layer.
Claim 12
Dependent Claim
43 words
The method of claim 5 further including forming a well of semiconductor material in said isolated semiconductor region, said well being of a different conductivity type semiconductor material than that of said isolated semiconductor region, and forming a PMOS circuit in said well.
Claim 13
Independent Claim
165 words
A method for fabricating a bipolar-CMOS circuit, comprising the steps of: forming on a P-type semiconductor substrate a number of N-type buried layers; forming on said substrate and on said buried layers an epitaxial layer of P-type semiconductor material; forming in said epitaxial layer a first and second N-type semiconductor well in electrical contact with a first and second said buried layers; forming a bipolar transistor in one said N-type semiconductor well; forming a PMOS transistor in a different said N-type semiconductor well; forming an N-type isolation ring around a region of said epitaxial layer and forming said N-type isolation ring in electrical contact with one said buried layers; forming an NMOS transistor in said isolated epitaxial layer; forming a CMOS circuit by interconnecting said PMOS transistor to said NMOS transistor; forming a backgate contact to said isolated epitaxial material of said NMOS transistor; and forming a different contact to said substrate so that said backgate and said substrate can be connected to different voltages.
Claim 14
Independent Claim
165 words
A method for fabricating a bipolar-CMOS circuit, comprising the steps of: forming on a P-type semiconductor substrate a number of N-type buried layers; forming on said substrate and on said buried layers an epitaxial layer of P-type semiconductor material; forming in said epitaxial layer a first and second N-type semiconductor well in electrical contact with a first and second said buried layers; forming a bipolar transistor in one said N-type semiconductor well; forming a PMOS transistor in a different said N-type semiconductor well; forming an N-type isolation ring around a region of said epitaxial layer and forming said N-type isolation ring in electrical contact with one said buried layers; forming an NMOS transistor in said isolated epitaxial layer; forming a CMOS circuit by interconnecting said PMOS transistor to said NMOS transistor; forming a backgate contact to said isolated epitaxial material of said NMOS transistor; and forming a different contact to said substrate so that said backgate and said substrate can be connected to different voltages.
Claim 15
Dependent Claim
31 words
The method of claim 11 further including forming a deep collector associated with said bipolar transistor and forming said deep collector in contact with a buried layer underlying said bipolar transistor.
Claim 16
Dependent Claim
22 words
The method of claim 12 further including forming said deep collector by the same process steps utilized in forming said isolation ring.
Claim 17
Dependent Claim
19 words
The method of claim 13 further including forming said deep collector substantially simultaneously as said isolation ring is formed.
Claim 18
Dependent Claim
17 words
The method of claim 11 further including forming an NPN transistor in said one N-type semiconductor well.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |