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US4910735A
Expired / Lapsed
US
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Semiconductor integrated circuit with self-testing
Assignee: Fujitsu Ltd
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Filing: 1987-12-17
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Granted: 1990-03-20
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Expires: 2007-12-17
Abstract
Abstract A semiconductor integrated circuit comprises a plurality of integrated circuit blocks constructed on a wafer. The integrated circuit blocks are electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a logic circuit for carrying out a logic operation, a pseudo-random pattern generating circuit for generating a pseudo-random pattern signal, a switching circuit for selecting either an input signal to be processed by the logic circuit or the pseudo-random pattern signal and a data compressing circuit for compressing an output data signal of the logic circuit. The switching circuit is responsive to a test enabling signal which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal mode, and outputs the selected signal to the logic circuit.
Inventors
- 👤 Koichi Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:44
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318335; G01R31/318385; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G01R31/318558; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
214 words
A semiconductor integrated circuit comprising: integrated circuit blocks connected in series for testing a system formed on said semiconductor integrated circuit, the system having a first stage and a following stage each including at least one of said integrated circuit blocks, each of said integrated circuit blocks comprising: logic means for carrying out a logic operation and providing output data signals corresponding thereto; an input terminal receiving input signals supplied to the integrated circuit blocks; pseudo-random pattern generating means for generating a pseudo-random pattern signal; data compressing means for receiving and compressing the output data signals supplied from said logic means to generate a compressed data signal; and an output terminal, operatively connected to said logic means, for receiving the output data signal from said logic means and for directly supplying the same to said input terminal of the integrated circuit blocks corresponding to the following stage, wherein at least one of said integrated circuit blocks of the first stage include first switching means for connecting said pseudo-random pattern generating means thereof to said logic means thereof during testing of the system, and wherein each of said integrated circuit blocks of the following stage include second switching means for connecting said input terminal thereof to said logic means thereof during testing of the system.
Claim 2
Dependent Claim
214 words
A semiconductor integrated circuit comprising: integrated circuit blocks connected in series for testing a system formed on said semiconductor integrated circuit, the system having a first stage and a following stage each including at least one of said integrated circuit blocks, each of said integrated circuit blocks comprising: logic means for carrying out a logic operation and providing output data signals corresponding thereto; an input terminal receiving input signals supplied to the integrated circuit blocks; pseudo-random pattern generating means for generating a pseudo-random pattern signal; data compressing means for receiving and compressing the output data signals supplied from said logic means to generate a compressed data signal; and an output terminal, operatively connected to said logic means, for receiving the output data signal from said logic means and for directly supplying the same to said input terminal of the integrated circuit blocks corresponding to the following stage, wherein at least one of said integrated circuit blocks of the first stage include first switching means for connecting said pseudo-random pattern generating means thereof to said logic means thereof during testing of the system, and wherein each of said integrated circuit blocks of the following stage include second switching means for connecting said input terminal thereof to said logic means thereof during testing of the system.
Claim 3
Dependent Claim
26 words
A circuit as recited in claim 1, wherein said semiconductor integrated circuit is a wafer-scale semiconductor integrated circuit, and said integrated circuit blocks comprise a wafer.
Claim 4
Dependent Claim
29 words
A circuit as recited in claim 1, wherein said logic means comprises a butterfly processor operatively connected to said input terminal thereof and said pseudo-random pattern generating means thereof.
Claim 5
Dependent Claim
23 words
A circuit as recited in claim 1, wherein said integrated circuit blocks of said semiconductor integrated circuit comprise a fast Fourier transform processor.
Claim 6
Dependent Claim
56 words
A circuit as recited in claim 1, wherein at least one of said integrated circuit blocks form a final stage, and the compressed data signal generated by said data compressing means of the at least one of said integrated circuit blocks of the final stage are used for determining whether said semiconductor integrated circuit operates correctly.
Claim 7
Dependent Claim
45 words
A circuit as recited in claim 1, wherein said semiconductor integrated circuit receives a plurality of test enable signals from an external circuit, and each of said first and second switching means comprises a test enable terminal for receiving one of the test enable signals.
Claim 8
Dependent Claim
57 words
A circuit as recited in claim 1, wherein said semiconductor integrated circuit operates in one of a test mode and a normal mode, and during the normal mode said first switching means corresponding to the at least one of said integrated circuit blocks of the first stage connects said input terminal thereof to said logic means thereof.
Claim 9
Dependent Claim
53 words
A circuit as recited claim 1, wherein said semiconductor integrated circuit operates in one of a test mode and a normal mode, and during the normal mode said second switching means corresponding to each of said integrated circuit blocks of the following stage connects said input terminal thereof to said logic means thereof.
Claim 10
Dependent Claim
41 words
A circuit as recited in claim 8, wherein during the normal mode said first switching means corresponding to the at least one of said integrated circuit blocks of the first stage connects said input terminal thereof to said logic means thereof.
Claim 11
Dependent Claim
25 words
A circuit as recited in claim 1, wherein said pseudorandom pattern generating means comprises a linear feedback shift register producing a cyclic redundancy check signal.
Claim 12
Dependent Claim
54 words
A wafer-scale integrated circuit for testing a complete system, said wafer-scale integrated circuit comprising logic blocks forming the complete system to be tested, each logic block including self-test means for testing said logic block corresponding thereto, said self-test means of at least one of said logic blocks is further for testing the complete system.
Claim 13
Dependent Claim
54 words
A wafer-scale integrated circuit for testing a complete system, said wafer-scale integrated circuit comprising logic blocks forming the complete system to be tested, each logic block including self-test means for testing said logic block corresponding thereto, said self-test means of at least one of said logic blocks is further for testing the complete system.
Claim 14
Dependent Claim
102 words
A circuit as recited in claim 11, wherein said logic blocks have an operational mode and a self-test mode, the complete system having a first stage and a following stage, wherein said wafer-scale integrated circuit further comprises means for providing test enable signals for independently switching each of said logic blocks between the self-test mode and the operational mode, and wherein during testing of the complete system at least one of said logic blocks in the first stage is switched into the self-test mode and at least one of said logic blocks in the following stage is switched into the operation mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |