Patent US4910708A successfully refreshed from Google Patents.
US4910708A
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Dram with programmable capacitance divider
Assignee: Ramtron International Corp
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Filing: 1989-01-03
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Granted: 1990-03-20
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Expires: 2009-01-03
Abstract
Abstract A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
Inventors
- 👤 S. Sheffield Eaton, Jr.
- 👤 Michael Parris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:21
CPC Classifications
G; G11; G11C; G11C14/00; G11C14/0054; G11C14/0072; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
162 words
In a DRAM having a memory cell comprising voltile and nonvolatile plortions, the improvement wherein: said volatile portion is responsively coupled to a word line and coupled to a bit line; said nonvolatile portion consists essentially of a capacitance divider including two ferroelectric capacitors couple together said divider including a common node coupled to plates of both of said ferroelectric capacitors and a pair of poles coupled to the other two plates of said capacitors; the memory cell further includes a circuit coupling said common node to said volatile DRAM memory cell portion; and the DRAM further comprises a signal generator located outside of the memory cell and providing a first variable signal and a second variable signal on first and second outputs, said first output being coupled to one pole of said divider, said second output being coupled to the second pole of said divider so that remanent polarization of ferroelectric material in said ferroelectric capacitors represents the nonvolatile stored data.
Claim 2
Dependent Claim
162 words
In a DRAM having a memory cell comprising voltile and nonvolatile plortions, the improvement wherein: said volatile portion is responsively coupled to a word line and coupled to a bit line; said nonvolatile portion consists essentially of a capacitance divider including two ferroelectric capacitors couple together said divider including a common node coupled to plates of both of said ferroelectric capacitors and a pair of poles coupled to the other two plates of said capacitors; the memory cell further includes a circuit coupling said common node to said volatile DRAM memory cell portion; and the DRAM further comprises a signal generator located outside of the memory cell and providing a first variable signal and a second variable signal on first and second outputs, said first output being coupled to one pole of said divider, said second output being coupled to the second pole of said divider so that remanent polarization of ferroelectric material in said ferroelectric capacitors represents the nonvolatile stored data.
Claim 3
Dependent Claim
32 words
The DRAM according to claim 1 wherein said coupling circuit comprises a switching device having a path of controllable conductivity coupled between said common node and said volatile DRAM memory cell portion.
Claim 4
Dependent Claim
38 words
The DRAM according to claim 2 wherein said switchable device comprises a field effect transistor having a source, drain, and gate, and wherein said source-drain path is coupled between said common node and said DRAM memory cell portion.
Claim 5
Dependent Claim
182 words
A dynamic RAM arrangement comprising a memory cell and a signal generator, the memory cell including first and second portions, the first portion comprising a volatile memory cell portion having a transistor coupled to a storage capacitor, and having an internal node between said storage capacitor and said transistor, said second portion being nonvolatile and comprising a capacitance divider formed by coupling first and second ferroelectric capacitors together to provide a common node coupled to plates of both of said ferroelectric capacitors and to provide first and second poles respectively coupled to the other two plates of said ferroelectric capacitors, the remanent polarization of the ferroelectric material in said ferroelectric capacitors representing the nonvolatile stored data, said common node in said second portion being coupled to said internal node in said first portion, said signal generator being coupled to provide a first variable signal (CLK3) and a second variable signal (CLK4) on first and second outputs, said first output being coupled to said first pole of said capacitance divider, said second output being coupled to said second pole of said capacitance divider.
Claim 6
Dependent Claim
182 words
A dynamic RAM arrangement comprising a memory cell and a signal generator, the memory cell including first and second portions, the first portion comprising a volatile memory cell portion having a transistor coupled to a storage capacitor, and having an internal node between said storage capacitor and said transistor, said second portion being nonvolatile and comprising a capacitance divider formed by coupling first and second ferroelectric capacitors together to provide a common node coupled to plates of both of said ferroelectric capacitors and to provide first and second poles respectively coupled to the other two plates of said ferroelectric capacitors, the remanent polarization of the ferroelectric material in said ferroelectric capacitors representing the nonvolatile stored data, said common node in said second portion being coupled to said internal node in said first portion, said signal generator being coupled to provide a first variable signal (CLK3) and a second variable signal (CLK4) on first and second outputs, said first output being coupled to said first pole of said capacitance divider, said second output being coupled to said second pole of said capacitance divider.
Claim 7
Dependent Claim
19 words
The DRAM arrangement of claim 4 further comprising a switchable device coupling said common node to said internal node.
Claim 8
Dependent Claim
29 words
The DRAM arrangement according to claim 5 wherein said switchable device comprises a field effect transistor having a source-drain path coupled between said internal node and said common node.
Claim 9
Dependent Claim
146 words
In a dynamic RAM memory arrangement of the type having a volatile dynamic RAM memory cell portion having an internal node (84) coupled to a bit line, and a nonvolatile memory cell portion coupled to the volatile memory cell portion, the improvement wherein the nonvolatile portion consists essentially of a ferroelectric capacitor divider comprising a pair of capacitors coupled together to form a common node (88) and a pair of poles (90, 92) said common node of said divider being coupled to said internal node, said divider including ferroelectric dielectric material, the improvement further comprising a signal generator located outside of said memory cell and coupled to provide at least one selectively variable voltage (CLK3) directly to one pole (90) of said divider and further comprising circuitry coupling a so that the remanent polarization of the dielectric in said capacitance divider indicates the nonvolatile stored data.
Claim 10
Dependent Claim
146 words
In a dynamic RAM memory arrangement of the type having a volatile dynamic RAM memory cell portion having an internal node (84) coupled to a bit line, and a nonvolatile memory cell portion coupled to the volatile memory cell portion, the improvement wherein the nonvolatile portion consists essentially of a ferroelectric capacitor divider comprising a pair of capacitors coupled together to form a common node (88) and a pair of poles (90, 92) said common node of said divider being coupled to said internal node, said divider including ferroelectric dielectric material, the improvement further comprising a signal generator located outside of said memory cell and coupled to provide at least one selectively variable voltage (CLK3) directly to one pole (90) of said divider and further comprising circuitry coupling a so that the remanent polarization of the dielectric in said capacitance divider indicates the nonvolatile stored data.
Claim 11
Dependent Claim
38 words
The improvement of claim 7 wherein said circuitry includes said generator which further provides a second selectively variable voltage (CLK4), and is coupled to provide said second variable voltage directly to the other pole (92) of said divider.
Claim 12
Dependent Claim
21 words
The improvement of claim 7 further comprising a switchable device (82) coupling said common node (88) to said internal node (84).
Claim 13
Dependent Claim
21 words
Te improvemen of claim 8 further comprising a switchable device (82) coupling said common node (88) to said internal node (84).
Claim 14
Dependent Claim
22 words
The improvement of claim 7 wherein each of said capacitors in said divider includes plates and ferroelectric dielectric material between the plates.
Claim 15
Dependent Claim
22 words
The improvement of claim 8 wherein each of said capacitors in said divider includes plates and ferroelectric dielectric material between the plates.
Claim 16
Dependent Claim
22 words
The improvement of claim 9 wherein each of said capacitors in said divider includes plates and ferroelectric dielectric material between the plates.
Claim 17
Dependent Claim
22 words
The improvement of claim 10 wherein each of said capacitors in said divider includes plates and ferroelectric dielectric material between the plates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |