US4910165A
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Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1988-11-04
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Granted: 1990-03-20
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Expires: 2008-11-04
Abstract
Abstract A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate. Planarization of the structure and exposure of the epitaxial surfaces provides electrically isolated islands of monocrystalline silicon for bipolar and field effect device fabrication. A CMOS implementation of the epitaxial islands is readily undertaken by selective counterdoping in the presence of a mask.
Inventors
- 👤 Steven S. Lee
- 👤 Dim-Lee Kwong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:15
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/191; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/117; Y10S148/152
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
107 words
A silicon on insulator fabrication process, comprising the steps of: forming onto a silicon substrate a layer of first material not conductive to epitaxial silicon formation; etching in the presence of a patterned mask through the layer of first material and into the substrate thereby forming walls, forming in said wells and in succession a materially doped epitaxial layer and a lightly doped epitaxial layer onto exposed substrate; selectively removing said layer of first material; selectively anodizing the materially doped epitaxial layer to make the layer porous; and oxidizing the porous epitaxial layer to form silicon dioxide electrically isolating the lightly doped epitaxial layer from the substrate.
Claim 2
Dependent Claim
107 words
A silicon on insulator fabrication process, comprising the steps of: forming onto a silicon substrate a layer of first material not conductive to epitaxial silicon formation; etching in the presence of a patterned mask through the layer of first material and into the substrate thereby forming walls, forming in said wells and in succession a materially doped epitaxial layer and a lightly doped epitaxial layer onto exposed substrate; selectively removing said layer of first material; selectively anodizing the materially doped epitaxial layer to make the layer porous; and oxidizing the porous epitaxial layer to form silicon dioxide electrically isolating the lightly doped epitaxial layer from the substrate.
Claim 3
Dependent Claim
24 words
The process recited in claim 1, wherein the materially doped epitaxial layer extends materially above a plane defined by the surface of the substrate.
Claim 4
Dependent Claim
13 words
The process recited in claim 2, wherein the first material is silicon dioxide.
Claim 5
Dependent Claim
13 words
The process recited in claim 2, wherein the first material is silicon nitride.
Claim 6
Dependent Claim
16 words
The process recited in claim 2, wherein the porosity of the anodized layer is approximately 50-60%.
Claim 7
Dependent Claim
41 words
The process recited in claim 5, wherein the oxidation step includes a low temperature oxidation to stabilize the porous epitaxial layer and a succeeding high temperature and oxygen ambient oxidation to convert substantially all the porous epitaxial layer to silicon dioxide.
Claim 8
Dependent Claim
41 words
The process recited in claim 5, wherein the oxidation step includes a low temperature oxidation to stabilize the porous epitaxial layer and a succeeding high temperature and oxygen ambient oxidation to convert substantially all the porous epitaxial layer to silicon dioxide.
Claim 9
Dependent Claim
28 words
The process recited in claim 7, including the additional step of planarizing the structure to fill the regions between the islands of lightly doped epitaxial layer with dielectric.
Claim 10
Dependent Claim
46 words
The process recited in claim 8, wherein the step of planarizing the structure includes filling regions between the epitaxial layer with undoped silicon and silicon dioxide, depositing a layer of planarizing material, and etching the structure to expose the surfaces of the lightly doped epitaxial layer.
Claim 11
Dependent Claim
152 words
A process for forming islands of monocrystalline silicon dielectrically isolated from the silicon substrate, comprising the steps of: forming a relatively thick layer of silicon dioxide in the substrate; anisotripically etching in the presence of a patterned mask through the silicon dioxide and into the substrate to form trenches; selectively growing epitaxial silicon from the exposed substrate in said trenches to form a first materially doped epitaxial layer extending to a level above a plane defined by the surface of the substrate; selectively growing onto the first epitaxial layer a second lightly doped epitaxial layer; selectively removing said silicon dioxide; selectively anodizing the first epitaxial layer to make the layer porous; selectively oxidizing the porous first epitaxial layer to form silicon dioxide isolating the second lightly doped epitaxial layer from the substrate; and planarizing the structure to fill the regions between the second lightly doped epitaxial layer with dielectric substantially coplanar therewith.
Claim 12
Dependent Claim
152 words
A process for forming islands of monocrystalline silicon dielectrically isolated from the silicon substrate, comprising the steps of: forming a relatively thick layer of silicon dioxide in the substrate; anisotripically etching in the presence of a patterned mask through the silicon dioxide and into the substrate to form trenches; selectively growing epitaxial silicon from the exposed substrate in said trenches to form a first materially doped epitaxial layer extending to a level above a plane defined by the surface of the substrate; selectively growing onto the first epitaxial layer a second lightly doped epitaxial layer; selectively removing said silicon dioxide; selectively anodizing the first epitaxial layer to make the layer porous; selectively oxidizing the porous first epitaxial layer to form silicon dioxide isolating the second lightly doped epitaxial layer from the substrate; and planarizing the structure to fill the regions between the second lightly doped epitaxial layer with dielectric substantially coplanar therewith.
Claim 13
Dependent Claim
24 words
The process recited in claim 3, wherein the substrate, materially doped epitaxial layer, and lightly doped epitaxial layer are of the same impurity type.
Claim 14
Dependent Claim
31 words
The process recited in claim 11, including the additional step of doping in the presence of a mask a selected lightly doped epitaxial layer region to change the impurity type thereof.
Claim 15
Dependent Claim
24 words
The process recited in claim 10, wherein the substrate, materially doped epitaxial layer, and lightly doped epitaxial layer are of the same impurity type.
Claim 16
Dependent Claim
30 words
The process recited in claim 13, including the additional step of doping in the presence of a mask a selected lightly doped epitaxial layer region to change the impurity thereof.
References Cited (Backward Citations)
US3640806A
Cited
US3919060A
Cited
US3954523A
Cited
US4016017A
Cited
US4104090A
Cited
JPS53136492A
Cited
JPS5420678A
Cited
JPS5420677A
Cited
US4393577A
Cited
US4380865A
Cited
JPS59144149A
Cited
US4604162A
Cited
JPS60144950A
Cited
US4628591A
Cited
JPS60242636A
Cited
US4810667A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |