Semiconductor memory device with improved output circuit

Claim 2

A semiconductor memory device having a plurality of memory cells arranged in rows and columns, a data bit read out from one of said memory cells being supplied to a pair of data lines, comprising: (a) a first sense amplifier circuit coupled to said data lines and operative to increase a difference in voltage level between said data lines for producing a data bit signal; (b) a first NOR gate activated by an output enable signal and coupled at an input node thereof to said first sense amplifier circuit for producing an inverted signal of said data bit signal; (c) a second sense amplifier circuit coupled to said data lines and operative to increase the difference in voltage level on said data lines for producing the inverse of said data bit signal; (d) a second NOR gate activated by said output enable signal and coupled at an input node thereof to said second sense amplifier circuit for producing a non-inverted signal of said data bit signal; and (e) an output inverter circuit responsive to said inverted signal and said non-inverted signal for producing an output data signal.

Claim 3

A semiconductor memory device as set forth in claim 1, in which each of said first and second NOR gate comprises a series combination of a first p-channel type field effect transistor and a complementary inverter circuit provided between a source of positive voltage and a ground terminal and a first n-channel type field effect transistor coupled between a common drain node of the complementary inverter circuit and the ground terminal, said first p-channel type field effect transistor and said first n-channel type field effect transistor having respective gate electrodes supplied with said output enable signal, said complementary inverter circuit being supplied with each of said data bit signal and the inverse thereof.

Claim 4

A semiconductor memory device as set forth in claim 1, in which each of said first and second NOR gates comprises a series combination of a first p-channel type field effect transistor and a complementary inverter circuit coupled between a source of positive voltage level and a ground terminal, a first n-channel type field effect transistor coupled between a common drain node of the complementary inverter circuit and the ground terminal, a series combination of a first n-p-n type bipolar transistor, an output node and a second n-p-n type field effect transistor coupled between the source of positive voltage level and the ground terminal, a series combination of a second n-channel type field effect transistor, a common drain node and a third n-channel type field effect transistor coupled between the output node and the ground terminal, and a fourth n-channel type field effect transistor coupled in parallel to the second n-channel type field effect transistor, said first p-channel type field effect transistor, said first and fourth n-channel type field effect transistors having respective gate electrodes supplied with said output enable signal, said complementary inverter circuit and said second n-channel type field effect transistor being supplied with said data bit signal, said third n-channel type field effect transistor having a gate electrode coupled to said output node, said first and second n-p-n type bipolar transistors having respective base electrodes coupled to common drain nodes of said complementary inverter circuit and said series combination of said second and third n-channel type field effect transistors, respectively, each of said inverted signal and said non-inverted signal being produced at said output node.

Claim 5

A semiconductor memory device as set forth in claim 3, in which each of said first and second sense amplifier circuits comprises a first series combination of a second p-channel type field effect transistor and a fifth n-channel type field effect transistor coupled between said source of positive voltage level and an activation node, a second series combination of a third p-channel type field effect transistor and a sixth n-channel type field effect transistor coupled between the source of positive voltage level and the activation node, and a seventh n-channel type field effect transistor coupled between the activation node and said ground terminal, said second and third p-channel type field effect transistors having respective gate electrodes coupled to a common drain node of said first series combination, said fifth and sixth n-channel type field effect transistors having respective gate electrodes coupled to said data lines, respectively, said second series combination having a common drain node where each of said data bit signal and the inverse thereof takes place.

Claim 6

A semiconductor memory device as set forth in claim 4, in which said output inverter circuit comprises a series combination of a third n-p-n type bipolar transistor and an eighth n-channel type field effect transistor coupled between said source of positive voltage level and said ground terminal and in which said inverted signal and said non-inverted signal are supplied to a base node of said third n-p-n type bipolar transistor and a gate electrode of said eighth n-channel type field effect transistor, respectively.