Computer control system and method for effecting sequence controls and servo-controls

Claim 2

A computer system for executing three types of parallel processing instructions including an open instruction, a close instruction and a pause instruction, said computer system comprising: a central processing unit (CPU); a timer comprising a counter renewed by a definite count at predetermined definite intervals and connected to said CPU to be read thereby; program memory means for storing programs of a sequence control and a servo-control to be executed by said CPU; a program counter connected to said CPU and said program memory means for designating an address of said program memory means, at which address an instruction to be executed next is stored, and a content of said program counter being renewed according to a type of instruction executed by said CPU; an address table connected to said CPU and said program counter for registering addresses of programs designated by an open instruction and a pause instruction, registered addresses of said address table being searched and erased in accordance with a close instruction; a time table connected to said CPU and written with a predetermined time from said timer for starting an execution of a program registered in said address table; and a pointer connected between said address table and said time table and to said CPU for scanning corresponding portions of said address table and said time table.

Claim 3

The computer control system according to claim 1, wherein the content of said program counter is renewed to an address of an instruction succeeding an open instruction, or to an address selected from said address table when a program containing an executed close instruction is terminated, or to an address of an instruction succeeding a close instruction or to an address selected by said address table in accordance with a pause instruction.

Claim 4

The computer control system according to claim 1, wherein in the case of said open instruction said address table is registered with an address of a program designated by an argument in a vacant portion of said address table found as a result of scanning of said address table by said pointer.

Claim 5

The computer system according to claim 1, wherein in the case of said pause instruction said address table is registered with an address of an instruction succeeding said pause instruction.

Claim 6

The computer system according to claim 1, wherein an address of a program designated by an argument and registered in said address table is written into an idle portion of said address table and erased as a result of scanning said address table by said pointer, in the case of said close instruction.

Claim 7

The computer system according to claim 1, wherein addresses registered in said address table are searched by said pointer and erased by a close instruction.

Claim 8

The computer system according to claim 1, wherein contents of said time table at positions designated by said pointer are transferred to said program counter under control of said CPU after executing said close or pause instruction, said CPU controlling said time table in accordance with an instruction read out from said program memory means.

Claim 9

The computer system according to claim 1, wherein said pointer is also used to read from and write into said address table and said time table.

Claim 10

The computer system according to claim 1, wherein said predetermined time corresponds to a count of said counter at the time of an open instruction or a sum of said count and a pause time designated by an argument of a pause instruction at the time of a pause instruction.

Claim 11

A computer system for effecting a sequence control and a servo-control, comprising: a central processing unit (CPU); an interruption clock which applies an interruption signal to said CPU at a predetermined interval; program memory means for storing programs of a sequence control and a servo-control to be executed by said CPU; a program counter connected to said CPU and said program memory means for designating an address of said program memory means, at which an instruction to be executed next is stored, and a content of said program counter being renewed according to a type of an instruction executed by said CPU; a plurality of service circuits connected to said CPU and said program counter, each service circuit including an address table connected to said program counter, a service pointer, a top pointer and a catalogue pointer, said pointers being connected to said address table; and a pause pointer controlled by said CPU for selecting one of said service circuits having a shortest pause time at an initial state, said address table being connected to said program counter for registering addresses of programs designated by an open instruction and a pause instruction, addresses registered in said address table and designated by said service pointer being transferred to said program counter; said service pointer designating a position of said address table storing an address of a program now being served; said top pointer denoting a leading address of a program to be served and stored in said address table; and said catalogue pointer denoting a position of said address table written by an open instruction and a pause instruction.

Claim 12

A computer system for effecting a sequence control and a servo-control, comprising: a central processing unit (CPU); an interruption clock which applies an interruption signal to said CPU at a predetermined interval; program memory means for storing programs of a sequence control and a servo-control to be executed by said CPU; a program counter connected to said CPU and said program memory means for designating an address of said program memory means, at which an instruction to be executed next is stored, and a content of said program counter being renewed according to a type of an instruction executed by said CPU; a plurality of service circuits connected to said CPU and said program counter, each service circuit including an address table connected to said program counter, a service pointer, a top pointer and a catalogue pointer, said pointers being connected to said address table; and a pause pointer controlled by said CPU for selecting one of said service circuits having a shortest pause time at an initial state, said address table being connected to said program counter for registering addresses of programs designated by an open instruction and a pause instruction, addresses registered in said address table and designated by said service pointer being transferred to said program counter; said service pointer designating a position of said address table storing an address of a program now being served; said top pointer denoting a leading address of a program to be served and stored in said address table; and said catalogue pointer denoting a position of said address table written by an open instruction and a pause instruction.

Claim 13

The computer system according to claim 10, wherein said CPU determines a time at which said interruption signal is applied so as to renew said pause pointer such that the same selects one of said service circuits in accordance with a pause time.

Claim 14

The computer system according to claim 10, wherein a content of said service pointer is renewed to a next position upon completion of programs now being served by a close instruction and a pause instruction.

Claim 15

The computer system according to claim 12, wherein when a renewed content of said service pointer coincides with a content of said top pointer, no program is executed and the content of said service pointer is renewed.

Claim 16

The computer system according to claim 10, wherein the service circuit containing a given top pointer is selected by said pause pointer, and a content of said top pointer is transferred to said service pointer.

Claim 17

The computer system according to claim 10, wherein the service circuit containing a given catalogue pointer is selected by said pause counter, and a content of said catalogue pointer is transferred to said top pointer.

Claim 18

The computer system according to claim 10, wherein said pause pointer is renewed when said interruption signal is applied to said CPU or when contents of said service pointer and said top pointer coincide with each other.