Semiconductor arrangement having at least one semiconductor body

Claim 2

A semiconductor arrangement comprising: at least first, second, third and fourth parallel electrically separated interconnects arranged on one and the same surface of a substrate; on the first interconnect a plurality of semiconductor bodies being arranged in a row and each semiconductor body being electrically connected to the first interconnect by a first contact; each of the semiconductor bodies having a second contact and a third contact, the second contacts being connected by first wires to the second interconnect and by second wires to the third interconnect, the third contacts being connected by third wires to the fourth interconnect, a first connecting lead and a second connecting lead being secured to portions of the first interconnect and the second interconnect, respectively, which lie adjacent to one another and parallel to one another; the first and second connecting leads located in close proximity, and at least partially parallel to one another, the first and second connecting leads being positioned at a right angle to the substrate surface; the third interconnect and the fourth interconnect connected to a first terminal and a second terminal, respectively.

Claim 3

The semiconductor arrangement according to claim 1, wherein the first and second interconnects of the first, second, third and fourth interconnects are each fashioned mirror-image symmetrical; wherein the semiconductor bodies are located on the second interconnect with symmetrically distribution; and wherein the connecting leads are connected to the corresponding interconnects on opposed sides of an axis of symmetry.

Claim 4

The semiconductor arrangement according to claim 1, wherein a space between the two connecting leads is filled with a dielectric which has a relative dielectric constant greater than one.

Claim 5

The semiconductor arrangement according to claim 3, wherein an insulator foil is arranged between the two connecting leads.

Claim 6

A semiconductor arrangement comprising: an insulating substrate; at least first, second, third and fourth parallel interconnects arranged on a same surface of the substrate and electrically separated from one another; a plurality of semiconductor bodies each having at least first, second and third contacts and located in a row on the first interconnect , the second contacts electrically connected to the second interconnect and to the third interconnect, and the third contacts electrically connected to the fourth interconnect, the semiconductor bodies being electrically connected to the first interconnect by the first contact; at least first and second connecting leads secured to the first and second interconnects, respectively, the connecting leads located in close proximity and at least partially parallel to one another, the two interconnects being parallel to one another and the connecting leads being secured to portions of the interconnects which lie adjacent and parallel to one another, the connecting leads being positioned at substantially a right angle to the surface of the substrate; the third interconnect and the fourth interconnect connected to a first terminal and a second terminal, respectively.

Claim 7

A semiconductor arrangement comprising: an insulating substrate; at least first, second, third and fourth parallel interconnects arranged on a same surface of the substrate and electrically separated from one another; a plurality of semiconductor bodies each having at least first, second and third contacts and located in a row on the first interconnect , the second contacts electrically connected to the second interconnect and to the third interconnect, and the third contacts electrically connected to the fourth interconnect, the semiconductor bodies being electrically connected to the first interconnect by the first contact; at least first and second connecting leads secured to the first and second interconnects, respectively, the connecting leads located in close proximity and at least partially parallel to one another, the two interconnects being parallel to one another and the connecting leads being secured to portions of the interconnects which lie adjacent and parallel to one another, the connecting leads being positioned at substantially a right angle to the surface of the substrate; the third interconnect and the fourth interconnect connected to a first terminal and a second terminal, respectively.

Claim 8

A semiconductor arrangement according to claim 5, wherein the first and second interconnects are configured with mirror-image symmetry about an axis of symmetry on the surface of the substrate, the plurality of semiconductor bodies located on the first interconnect arranged symmetrically thereon about the axis of symmetry, and wherein the first and second connecting leads are connected to the corresponding first and second interconnects on opposed sides of the axis of symmetry.

Claim 9

A semiconductor arrangement according to claim 5, wherein a space between the two connecting leads is filled with a dielectric which has a relative dielectric constant greater than one.

Claim 10

A semiconductor arrangement according to claim 7, wherein an insulator foil is arranged between the two connecting leads.