Semiconductor memory device capable of selective operation of memory cell blocks

Claim 1

A semiconductor memory device including row decoders and column decoders, comprising: a memory cell array including a plurality of memory cell blocks, each of said memory cell blocks being respectively operatively connected to one of the row decoders and one of the column decoders; clock generator means including a plurality of clock generator sections, each of said clock generator sections corresponding to one of said memory cell blocks and each of said clock generator sections sequentially generating a plurality of clock signals for driving corresponding memory cell blocks; address drive generator means for generating an address drive signal; address buffer means, coupled to said address drive generator means, for receiving the address drive signal and outputting address bit signals; and block selector means, coupled to said clock generator means, for selecting one of said clock generator sections in correspondence with the row address of a designated address and causing clock signals of only said selected clock generator section to be output for operating a corresponding one of said memory cell blocks, said block selector means comprising: a plurality of two-input logic gates having first input terminals for receiving address drive signals from said address drive generator, means, and second input terminals for receiving address bit signals from said address buffer, whereby only a clock generator section corresponding to said selected memory cell block is operated by said designated address.