US4905172A
Expired / Lapsed
US
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Method of generating and transmitting digitally distorted test signals
Assignee: Tektronix Inc
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Filing: 1988-07-21
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Granted: 1990-02-27
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Expires: 2008-07-21
Abstract
Abstract A microprocessor controlled test system generates and transmits distorted digital signals to a system under test by expanding a bit pattern, representative of a character to be transmitted, by an integer multiple of expansion. Selected bits of the expanded bit pattern are toggled from one logic level to another under program control to produce a distorted expanded bit pattern. The distorted expanded bit pattern is clocked out of the test system to the system under test at a rate equal to the integer multiple of expansion times the baud rate of the system under test. The resolution of the test signal can be varied by changing the integer multiple of expansion along with the rate at which the test signal is clocked out of the test system. The invention is useful in testing and adjusting a teletypewriter.
Inventors
- 👤 William C. Randle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:18
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24; H04L1/242; H04L1/244
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
102 words
A method of generating and transmitting a distorted digital signal to a system under test having a known baud rate, the steps comprising: generating a bit pattern representative of input data to be sent to said system under test; expanding each bit of said bit pattern by an integer multiple to create an expanded bit pattern representative of said input data; toggling selected bits of said expanded bit pattern to create an altered expanded bit pattern representative of said input data with distortion added thereto; and transmitting said altered expanded bit pattern as said distorted digital signal to said system under test.
Claim 2
Independent Claim
102 words
A method of generating and transmitting a distorted digital signal to a system under test having a known baud rate, the steps comprising: generating a bit pattern representative of input data to be sent to said system under test; expanding each bit of said bit pattern by an integer multiple to create an expanded bit pattern representative of said input data; toggling selected bits of said expanded bit pattern to create an altered expanded bit pattern representative of said input data with distortion added thereto; and transmitting said altered expanded bit pattern as said distorted digital signal to said system under test.
Claim 3
Dependent Claim
59 words
The method of claim 1 for generating and transmitting a distorted digital signal to a system under test wherein said step of generating said bit pattern representative of input data comprises the further steps of: receiving parameters for initiating a series of programmed steps to generate said bit pattern; and storing said generated bit pattern in a RAM memory.
Claim 4
Dependent Claim
90 words
The method of claim 1 for generating and transmitting a distorted digital signal to a system under test wherein said expansion of each said bit of said bit pattern by an integer multiple comprises the addition steps of: selecting the integer multiple by which each said bit of said bit pattern will be expanded; creating for each said bit of said bit pattern a like number of bits equal in number to said integer multiple; and storing in a RAM memory said created bit patterns forming said expanded bit pattern.
Claim 5
Dependent Claim
69 words
The method of claim 3 for generating and transmitting a distorted digital signal to a system under test wherein said step of toggling selected bits of said expanded bit pattern further comprises the steps of: determining a percentage of distortion to be added to said created bit patterns; and changing a portion of said created bit patterns to match said percentage of distortion forming said altered expanded bit pattern.
Claim 6
Dependent Claim
85 words
The method of claim 1 for generating and transmitting a distorted digital signal to a system under test wherein said step of transmitting said altered expanded bit pattern comprises the additional steps of: reading out from a RAM memory in parallel format said altered expanded bit pattern; converting said parallel formatted altered expanded bit pattern into serial data; and transmitting said serial data to said system under test at a rate equal to the baud rate of said system under test and said integer multiple.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-26 | 1993-08-28 | 1994-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-26 | 1997-08-28 | 1998-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-26 | 2001-08-28 | 2002-02-27 | $7700.00 | Window Closed / Lapsed |