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Patent US4904886A successfully refreshed from Google Patents.
US4904886A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate array with high driving ability cells
Assignee: NEC Corp
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Filing: 1988-07-20
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Granted: 1990-02-27
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Expires: 2008-07-20
Abstract
Abstract A gate array for implementing a digital integrated circuit includes first cells and second cells of different kinds which are selectively usable depending upon the application of the gate array, i.e. the first cells for applications which need only a low driving ability and the second cells for applications which need a high driving ability.
Inventors
- 👤 Toshio Tanahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H10; H10D; H10D84/00; H10D84/90; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
115 words
A gate array comprising: a logic area having a first cell and a second cell which is greater in area than said first cell by an integral multiple, wherein said first cell comprises a first transistor group, a first resistor group, and first wiring regions, and said second cell comprises a second transistor group, a second resistor group, and second wiring regions, and wherein said second transistor group is larger than said first transistor group, and said second resistor group has a resistance value lower than a resistance value of said first resistor group; and an input/output buffer area surrounding said logic area for interfacing said logic area to the outside for interchange of signals.
Claim 2
Dependent Claim
115 words
A gate array comprising: a logic area having a first cell and a second cell which is greater in area than said first cell by an integral multiple, wherein said first cell comprises a first transistor group, a first resistor group, and first wiring regions, and said second cell comprises a second transistor group, a second resistor group, and second wiring regions, and wherein said second transistor group is larger than said first transistor group, and said second resistor group has a resistance value lower than a resistance value of said first resistor group; and an input/output buffer area surrounding said logic area for interfacing said logic area to the outside for interchange of signals.
Claim 3
Dependent Claim
23 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said first resistor group have a same resistance value.
Claim 4
Dependent Claim
23 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said second resistor group have a same resistance value.
Claim 5
Dependent Claim
25 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said first resistor group have different resistance values from each other.
Claim 6
Dependent Claim
25 words
A gate array as claimed in claim 1, wherein a plurality of resistors consituting said second resistor group have different resistance values from each other.
Claim 7
Dependent Claim
35 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said first resistor group are disposed in an area different from an area in which said first transistor group is disposed.
Claim 8
Dependent Claim
35 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said second resistor group are disposed in an area different from an area in which said second transistor group is disposed.
Claim 9
Dependent Claim
31 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said first resistor group are distributed in an area in which said first transistor group is disposed.
Claim 10
Dependent Claim
31 words
A gate array as claimed in claim 1, wherein a plurality of resistors constituting said second resistor group are distributed in an area in which said second transistor group is disposed.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-26 | 1993-08-28 | 1994-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-26 | 1997-08-28 | 1998-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-26 | 2001-08-28 | 2002-02-27 | $7700.00 | Window Closed / Lapsed |