US4566022A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flexible/compressed array macro design
Assignee: International Business Machines Corp
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Filing: 1983-01-27
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Granted: 1986-01-21
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Expires: 2003-01-27
Abstract
Abstract A transistor array arrangement for providing high-density semiconductor logic circuits in double polysilicon technology is described. Semiconductor, for example, FET, logic circuits have four independent but simultaneously accessible FET devices which are formed by intersecting sets of polysilicon gate lines. The four FET devices share a common first diffusion, for example a source, surrounded by four logically independent second diffusions, for example drains. A three-bit decode device is made which includes this array design.
Inventors
- 👤 Howard L. Kalter
- 👤 Donald B. Kiley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:36
CPC Classifications
H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
110 words
An integrated circuit logic device comprising a semiconductor substrate of a first conductivity type having a plurality of second conductivity type regions in a surface thereof; said second conductivity type regions being bounded at least partially by at least two sets of intersecting conductive gate means which serve as input means to form a plurality of FET devices, at least some of which have one of said second regions as a common first current conducting electrode; and at least three of the remaining second regions adjacent to said one second region forming the second current conducting electrode of three FET devices; said second regions not being connected to each other.
Claim 2
Dependent Claim
110 words
An integrated circuit logic device comprising a semiconductor substrate of a first conductivity type having a plurality of second conductivity type regions in a surface thereof; said second conductivity type regions being bounded at least partially by at least two sets of intersecting conductive gate means which serve as input means to form a plurality of FET devices, at least some of which have one of said second regions as a common first current conducting electrode; and at least three of the remaining second regions adjacent to said one second region forming the second current conducting electrode of three FET devices; said second regions not being connected to each other.
Claim 3
Dependent Claim
49 words
A device as described in claim 1 including a fourth of the remaining second regions adjacent to said one second region forming the second current conducting electrode of a fourth FET device; said fourth of the remaining second regions not being connected to any other of said second regions.
Claim 4
Dependent Claim
27 words
A device as described in claim 1 including a third set of intersecting conductive means connected to said second conductivity type regions which serve as output means.
Claim 5
Dependent Claim
18 words
A device as described in claim 1 wherein said sets of conductive gate means are made of polysilicon.
Claim 6
Dependent Claim
19 words
A device as described in claim 4 wherein said polysilicon is in two layers separated by an insulative layer.
Claim 7
Dependent Claim
117 words
A three-bit decode device comprising a semiconductor substrate of a first conductivity type having a plurality of second type conductivity type regions in a surface thereof; three sets of intersecting conductive gate means positioned about said second conductivity type regions to form a plurality of FET devices, at least some of said FET devices having one of said second regions as a common first current conducting electrode, two sets of said intersecting means serving as input means and one set as output means; and at least three of the remaining second regions adjacent to said one second region forming the second current conducting electrode of three FET devices; said second regions not being connected to each other.
Claim 8
Dependent Claim
117 words
A three-bit decode device comprising a semiconductor substrate of a first conductivity type having a plurality of second type conductivity type regions in a surface thereof; three sets of intersecting conductive gate means positioned about said second conductivity type regions to form a plurality of FET devices, at least some of said FET devices having one of said second regions as a common first current conducting electrode, two sets of said intersecting means serving as input means and one set as output means; and at least three of the remaining second regions adjacent to said one second region forming the second current conducting electrode of three FET devices; said second regions not being connected to each other.
Claim 9
Dependent Claim
49 words
A device as described in claim 6 including a fourth of the remaining second regions adjacent to said one second region forming the second current conducting electrode of a fourth FET device; said fourth of the remaining second regions not being connected to any other of said second regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-20 | 1989-07-22 | 1990-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-20 | 1993-07-22 | 1994-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-20 | 1997-07-22 | 1998-01-21 | $7700.00 | Window Closed / Lapsed |