Field effect transistor

Claim 2

A field effect transistor, comprising a body of semiconductive material a plurality of regions of one conductivity type of said semiconductor material adjacent one major planar surface of said body, said plurality of regions constituting an array of source and drain regions alternating along a line of centers in each of mutually perpendicular directions along said surface, a gate overlying a plurality of intersecting channels of said field effect transistor, said channels being of like conductivity type to said one conductivity type and each constituting a strip bounded on one side by a source region and on the other side by a drain region, and first and second means each partially in the form of parallel spaced-apart interconnected conductive fingers, said first means having its fingers disposed at an angle to said line of centers and conductively interconnecting said source regions together, said second means having at least some of its fingers disposed between the fingers of said first means and conductively interconnecting said drain regions together.

Claim 3

The field effect transistor of claim 1 wherein said gate comprises a region of said semiconductor material of opposite conductivity type conforming in pattern to said intersecting channels and disposed between said source and drain regions adjacent said surface.

Claim 4

The field effect transistor of claim 1, wherein each of said first and second means further includes a distinct and different contact formed in each of said source and drain regions, the respective set of conductive fingers comprising a metallization pattern interconnecting the respective contacts in the source and drain regions.

Claim 5

The field effect transistor of claim 3 wherein each of said contacts is located at substantially the center of the respective region, at said one surface.

Claim 6

The field effect transistor of claim 2 wherein said gate forms a substantially rectangular pattern of intersecting lines.

Claim 7

The field effect transistor of claim 5 wherein at least some of said source and drain regions are substantially square in shape at said surface.

Claim 8

A field effect transistor, comprising a body of semiconductor material, a plurality of spaced-apart source and drain regions alternating in two mutually perpendicular directions along a major planar surface of and within said body, strip-like regions of semiconductor material of said body between each pair of source and drain regions forming a plurality of intersecting channels separating the source and drain regions for current flow therebetween, and a gate underlying and generally conforming to the pattern of said plurality of intersecting channels for selectively controlling the magnitude of said Current flow.

Claim 9

A field effect transistor, comprising a body of semiconductor material, a plurality of spaced-apart source and drain regions alternating in two mutually perpendicular directions along a major planar surface of and within said body, strip-like regions of semiconductor material of said body between each pair of source and drain regions forming a plurality of intersecting channels separating the source and drain regions for current flow therebetween, and a gate underlying and generally conforming to the pattern of said plurality of intersecting channels for selectively controlling the magnitude of said Current flow.

Claim 10

A field effect transistor, comprising a body of semiconductor material, a plurality of source and drain regions formed in spaced-apart relationship in said body adjacent a major surfacing thereof and alternating in two distinct and different directions along said surface, said source and drain regions being of generally rectangular shape at said surface and each source region having an edge parallel to and coextensive with an edge of the adjacent drain region, said source regions being electrically interconnected and said drain regions being electrically interconnected separately from said source regions such that upon proper biasing of the source and drain regions via the electrical interconnects a current flow is established in a strip-like channel of semiconductor material between each source region and an adjacent drain region, the cumulative current contributions appearing at the electrical interconnection of the drain regions, and a gate in the form of a network of intersecting interconnected paths overlying the channels and conforming to the shape thereof to control, when electrically biased, the magnitude of the current flow in said channels.

Claim 11

A field effect transistor, comprising a body of semiconductor material, a plurality of source and drain regions formed in spaced-apart relationship in said body adjacent a major surfacing thereof and alternating in two distinct and different directions along said surface, said source and drain regions being of generally rectangular shape at said surface and each source region having an edge parallel to and coextensive with an edge of the adjacent drain region, said source regions being electrically interconnected and said drain regions being electrically interconnected separately from said source regions such that upon proper biasing of the source and drain regions via the electrical interconnects a current flow is established in a strip-like channel of semiconductor material between each source region and an adjacent drain region, the cumulative current contributions appearing at the electrical interconnection of the drain regions, and a gate in the form of a network of intersecting interconnected paths overlying the channels and conforming to the shape thereof to control, when electrically biased, the magnitude of the current flow in said channels.

Claim 12

The field effect transistor of claim 7, wherein said source and drain regions and said channels are of one conductivity type, and said gate is of opposite conductivity type, and further including another gate supporting said source and drain regions and said channels and being coextensive therewith within said body, said another gate separated from said first gate by said channels.

Claim 13

The field effect transistor of claim 9, wherein separate source and drain contacts are formed in respective ones of said source and drain regions.

Claim 14

The field effect transistor of claim 10, further including a first metal layer overlying said surface and electrically interconnecting said source contacts, and a second metal layer electrically isolated from the first, further overlying said surface and electrically interconnecting said drain contacts.

Claim 15

The field effect transistor of claim 11, wherein said channels and said first gate form a rectangular grid of intersecting lines.