US4904885A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Substrate bias circuit having substrate bias voltage clamp and operating method therefor
Assignee: Mitsubishi Electric Corp
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Filing: 1988-06-06
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Granted: 1990-02-27
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Expires: 2008-06-06
Abstract
Abstract A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.
Inventors
- 👤 Michihiro Yamada
- 👤 Hiroshi Miyamoto
- 👤 Tadato Yamagata
- 👤 Shigeru Mori
- 👤 Tetsuya Aono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
For a semiconductor device including a semiconductor substrate on which field effect transistors are formed, said device including a power supply terminal, a ground terminal and a substrate bias terminal, parasitic capacitance tending to be formed between said power supply terminal and said substrate bias terminal, said device further including a substrate bias generating circuit coupled to said power supply terminal and said ground terminal for generating a substrate bias voltage having a predetermined value and applying said substrate bias voltage to said substrate bias terminal, a substrate bias voltage clamp circuit, comprising: switching means connected between said substrate bias terminal and said ground terminal, said switching means including a control electrode for controlling said switching means to be on or off, selectively; and control means coupled to said control electrode and responsive to a change of voltage at said power supply terminal for turning said switching means on for a predetermined time duration; said control means including (a) capacitor means connected between said power supply terminal and said control electrode, and (b) discharge means for discharging said capacitor means, (c) said predetermined time duration being established by a discharge time of said capacitor means by said discharge means.
Claim 2
Dependent Claim
199 words
For a semiconductor device including a semiconductor substrate on which field effect transistors are formed, said device including a power supply terminal, a ground terminal and a substrate bias terminal, parasitic capacitance tending to be formed between said power supply terminal and said substrate bias terminal, said device further including a substrate bias generating circuit coupled to said power supply terminal and said ground terminal for generating a substrate bias voltage having a predetermined value and applying said substrate bias voltage to said substrate bias terminal, a substrate bias voltage clamp circuit, comprising: switching means connected between said substrate bias terminal and said ground terminal, said switching means including a control electrode for controlling said switching means to be on or off, selectively; and control means coupled to said control electrode and responsive to a change of voltage at said power supply terminal for turning said switching means on for a predetermined time duration; said control means including (a) capacitor means connected between said power supply terminal and said control electrode, and (b) discharge means for discharging said capacitor means, (c) said predetermined time duration being established by a discharge time of said capacitor means by said discharge means.
Claim 3
Dependent Claim
61 words
The circuit of claim 1, wherein said switching means comprises a field effect transistor connected between said substrate bias terminal and said ground terminal having a gate electrode; said capacitor means includes a capacitor connected between said power supply terminal and said gate electrode; and said discharge means includes a resistor connected between said substrate bias terminal and said gate electrode.
Claim 4
Dependent Claim
92 words
The circuit of claim 2, wherein said switching means comprises a first field effect transistor connected between said substrate bias terminal and said ground terminal and having a gate electrode; said capacitor means includes a capacitor connected between said power supply terminal and said gate electrode of said first field effect transistor; and said discharge means includes a second field effect transistor connected between said substrate bias terminal and said gate electrode of said first field effect transistor; said second field effect transistor having a gate connected to said power supply terminal.
Claim 5
Dependent Claim
114 words
The circuit of claim 1, wherein said switching means comprises a first field effect transistor connected between said substrate bias terminal and said ground terminal and having a gate electrode; said capacitor means includes a capacitor connected between said power supply terminal and said gate electrode; and said discharge means including (a) a potential divider means connected between said power supply terminal and said ground terminal; and (b) a second field effect transistor connected between the gate electrode of said first field effect transistor and said substrate bias terminal and having a gate electrode; said gate electrode of said second field effect transistor being connected to an output node of said potential divider means.
Claim 6
Dependent Claim
170 words
For a semiconductor device including a semiconductor substrate on which field effect transistors are formed, said device including a power supply terminal, a ground terminal and a substrate bias terminal, parasitic capacitance tending to be formed between said power supply terminal and said substrate bias terminal, said device further including a substrate bias generating circuit for generating a substrate bias voltage having a predetermined value and applying said substrate bias voltage to said substrate bias terminal, a substrate bias voltage clamp circuit, comprising: switching means connected between said substrate bias terminal and said ground terminal, said switching means including a control electrode for controlling said switching means to be on or off, selectively; capacitor means connected between said power supply terminal and said control electrode for turning on said switching means in response to a voltage change at said power supply terminal; and discharge means for discharging said capacitor means to turn off said switching means following a time duration determined by values of capacitor means and said discharge means.
Claim 7
Dependent Claim
170 words
For a semiconductor device including a semiconductor substrate on which field effect transistors are formed, said device including a power supply terminal, a ground terminal and a substrate bias terminal, parasitic capacitance tending to be formed between said power supply terminal and said substrate bias terminal, said device further including a substrate bias generating circuit for generating a substrate bias voltage having a predetermined value and applying said substrate bias voltage to said substrate bias terminal, a substrate bias voltage clamp circuit, comprising: switching means connected between said substrate bias terminal and said ground terminal, said switching means including a control electrode for controlling said switching means to be on or off, selectively; capacitor means connected between said power supply terminal and said control electrode for turning on said switching means in response to a voltage change at said power supply terminal; and discharge means for discharging said capacitor means to turn off said switching means following a time duration determined by values of capacitor means and said discharge means.
Claim 8
Dependent Claim
62 words
The circuit of claim 5, wherein said switching means comprises a field effect transistor connected between said substrate bias terminal and said ground terminal and having a gate electrode; said capacitor means includes a capacitor connected between said power supply terminal and said gate electrode; and said discharge means includes a resistor connected between said substrate bias terminal and said gate electrode.
Claim 9
Dependent Claim
92 words
The circuit of claim 5, wherein said switching means comprises a first field effect transistor connected between said substrate bias terminal and said ground terminal and having a gate electrode; said capacitor means includes a capacitor connected between said power supply terminal and said gate electrode of said first field effect transistor; and said discharge means includes a second field effect transistor connected between said substrate bias terminal and said gate electrode of said first field effect transistor; said second field effect transistor having a gate connected to said power supply terminal.
Claim 10
Dependent Claim
114 words
The circuit of claim 5, wherein said switching means comprises a first field effect transistor connected between said substrate bias terminal and said ground terminal and having a gate electrode; said capacitor means includes a capacitor connected between said power supply terminal and said gate electrode; and said discharge means including (a) a potential divider means connected between said power supply terminal and said ground terminal; and (b) a second field effect transistor connected between the gate electrode of said first field effect transistor and said substrate bias terminal and having a gate electrode; said gate electrode of said second field effect transistor being connected to an output node of said potential divider means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-26 | 1993-08-28 | 1994-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-26 | 1997-08-28 | 1998-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-26 | 2001-08-28 | 2002-02-27 | $7700.00 | Window Closed / Lapsed |