Integrated circuit comprising a latch-up protection circuit in complementary MOS-circuitry technology

Claim 2

An integrated circuit, comprising: a doped semiconductor substrate; complementary MOS-circuitry in the substrate; a substrate bias voltage terminal in the doped semiconductor substrate connected to an output of a substrate bias voltage generator; a capacitor having first and second capacitor surfaces, the first capacitor surface being integrated in the doped semiconductor substrate, and the second capacitor surface being connected via an electronic protection circuit means to a capacitor bias voltage generator; and said electronic protection circuit means interconnecting the second capacitor surface and the capacitor bias voltage generator following a delay time ΔT when the integrated circuit is switched on.

Claim 3

An integrated circuit according to claim 1 wherein a well-like semiconductor zone is provided in the substrate.

Claim 4

An integrated circuit according to claim 2 wherein the substrate is of first conductivity type, a well-like zone is of second conductivity type, the well-like zone has a first conductivity type channel FET therein, and the substrate has a second conductivity type channel FET therein outside of said well-like zone together with a storage cell formed of a second conductivity type channel FET connecting to said capacitor.

Claim 5

An integrated circuit according to claim 2 wherein the well-like zone encompasses the substrate bias voltage terminal and said capacitor, and wherein a storage cell is provided formed of an FET connecting to said capacitor, and wherein at least one further FET is provided of one conductivity type within said well-like zone and another FET of an opposite conductivity type is provided outside of said well-like zone.

Claim 6

An integrated circuit according to claim 1 wherein the electronic protection circuit means comprises a timer connecting to an electronic switch through an amplifier.

Claim 7

An integrated circuit according to claim 5 wherein the timer has a series connection of a load element and a first field effect transistor, a first terminal at one end of this series arrangement which is a terminal of the load element being connected to a positive voltage, and a second terminal of this series arrangement which comprises source, drain, and substrate terminals of the first field effect transistor being connected to ground potential.

Claim 8

An integrated circuit according to claim 6 wherein the electronic switch has an n-channel field effect transistor whose gate terminal is connected to a connection point of the first field effect transistor and the load element of the series arrangement, a substrate terminal of the n-channel field effect transistor being connected to a negative voltage, a source terminal of the n-channel field effect transistor being connected to the second capacitor surface, and a drain terminal of the n-channel field effect transistor being connected to the capacitor bias voltage generator.

Claim 9

An integrated circuit according to claim 6 wherein the load element is formed by a second field effect transistor of a channel type different than a channel type of the first field effect transistor, a gate terminal of the second field effect transistor being connected to the ground potential, and a substrate terminal of the second field effect transistor being connected to the positive voltage.

Claim 10

An integrated circuit according to claim 5 wherein the timer has a series arrangement of a load element and a first field effect transistor, a first terminal of said series arrangement which comprises source, drain, and substrate terminals of the first field effect transistor being connected to a positive voltage, and a second terminal of said series arrangement which is a terminal of the load element is connected to ground potential.

Claim 11

An integrated circuit according to claim 9 wherein the electronic switch has a p-channel field effect transistor, a gate terminal of the p-channel field effect transistor being connected to a connection point of the first field effect transistor and the load element of the series arrangement, a substrate terminal of the p-channel field effect transistor being connected to the positive voltage, a drain terminal of the p-channel field effect transistor being connected to the second capacitor surface, and a source terminal of the p-channel field effect transistor being connected to the capacitor bias voltage generator.

Claim 12

An integrated circuit according to claim 9 wherein the load element is formed of a field effect transistor of a channel type different than a channel type of the first field effect transistor, a gate terminal of the field effect transistor being connected to the positive voltage and a substrate terminal of the field effect transistor being connected to a negative voltage.

Claim 13

An integrated circuit according to claim 1 wherein the output of the substrate bias voltage generator is connected via an electronic switch to a circuit point at ground potential, and the electronic switch is driven via a voltage obtained from the substrate bias voltage terminal.

Claim 14

An integrated circuit according to claim 1 wherein the substrate bias voltage generator, the capacitor bias voltage generator, and the electronic protection circuit means are co-integrated on the semiconductor substrate.

Claim 15

An integrated circuit according to claim 1 wherein densely integrated dynamic semiconductor memories are provided in the substrate.

Claim 16

An integrated circuit, comprising: a substrate having at least a first FET of first channel conductivity type and a complementary second FET of second conductivity type, and a well-like zone in the substrate containing one of said first and second FETs; a storage cell in the substrate formed of a third FET connected to a capacitor having first and second surfaces, the first surface being a doped region surrounded by the substrate and a second surface overlying the first surface; a substrate bias voltage terminal in the substrate; a substrate bias voltage generator connected at one side to a supply voltage and at the other side to said substrate bias voltage terminal; a bias voltage generator connected at one side to a supply voltage and at an opposite side through an electronic protection circuit to said second surface of the capacitor; and said electronic protection circuit having means for interconnecting the second capacitor surface and the capacitor bias voltage generator following a delay time ΔT when the integrated circuit is activated.

Claim 17

An integrated circuit, comprising: a substrate having at least a first FET of first channel conductivity type and a complementary second FET of second conductivity type, and a well-like zone in the substrate containing one of said first and second FETs; a storage cell in the substrate formed of a third FET connected to a capacitor having first and second surfaces, the first surface being a doped region surrounded by the substrate and a second surface overlying the first surface; a substrate bias voltage terminal in the substrate; a substrate bias voltage generator connected at one side to a supply voltage and at the other side to said substrate bias voltage terminal; a bias voltage generator connected at one side to a supply voltage and at an opposite side through an electronic protection circuit to said second surface of the capacitor; and said electronic protection circuit having means for interconnecting the second capacitor surface and the capacitor bias voltage generator following a delay time ΔT when the integrated circuit is activated.