Real space electron transfer device using hot electron injection

Claim 2

A semiconductor device comprising three semiconductor regions which are spatially sequential in a first direction, and which here are designated, in sequence, as first channel region, potential-barrier region, and second channel region, said first and second channel regions having respective first and second bandgaps, and said potential-barrier region having a composition adapted to forming a potential barrier between said first and second channel regions; means for supplying carriers to said first and second channel regions; first and second contacts to said first channel region, said first and second contacts being spaced apart in a second direction which is perpendicular to said first direction, and said first and second contacts being such as not to make contact to said second channel region; and a third contact to said second channel region.

Claim 3

The device of claim 1, said potential-barrier region having a third bandgap which is greater than said first and second bandgaps.

Claim 4

The device of claim 2, said third bandgap decreasing with increasing distance from said first channel region.

Claim 5

The device of claim 1, said device comprising a gate electrode to said first channel region.

Claim 6

The device of claim 1, said device comprising a gate electrode to said second channel region.

Claim 7

The device of claim 1, the material of said semiconductor regions being selected from the group consisting of Si, Ge, Group II-VI, and Group III-V semiconductor materials.

Claim 8

The device of claim 6, said Group III-V compound semiconductor materials comprising InAlAs and InGaAs.

Claim 9

The device of claim 1, said potential-barrier region comprising a heavily doped composition.

Claim 10

A logic element comprising two series-connected semiconductor devices, each of said devices comprising three semiconductor regions which are spatially sequential in a first direction, and which here are designated, in sequence, as first channel region, potential-barrier region, and second channel region, said first and second channel regions having respective first and second bandgaps, and said potential-barrier region having a composition adapted to forming a potential barrier between said first and second channel regions; means for supplying carriers to said first and second channel regions; first and second contacts to said first channel region, said first and second contacts being spaced apart in a second direction which is perpendicular to said first direction, and said first and second contacts being such as not to make contact to said second channel region; and a third contact to said second channel region.

Claim 11

A logic element comprising two series-connected semiconductor devices, each of said devices comprising three semiconductor regions which are spatially sequential in a first direction, and which here are designated, in sequence, as first channel region, potential-barrier region, and second channel region, said first and second channel regions having respective first and second bandgaps, and said potential-barrier region having a composition adapted to forming a potential barrier between said first and second channel regions; means for supplying carriers to said first and second channel regions; first and second contacts to said first channel region, said first and second contacts being spaced apart in a second direction which is perpendicular to said first direction, and said first and second contacts being such as not to make contact to said second channel region; and a third contact to said second channel region.