Subranging analog-to-digital converter with digital error correction

Claim 2

An analog-to-digital conversion system for converting an analog input signal into corresponding digital output values, said conversion system comprising: first means for converting an instantaneous value of the analog input signal into a first digital value; second means for converting said first digital value into a first intermediate analog value; difference means for providing a second intermediate analog value which is responsive to the difference between said instantaneous value of the analog input signal and the first intermediate analog value; third means for converting said second intermediate analog value into a second digital value; correction means for providing a predetermined correction value responsive to said first digital value, said correction means including a digital memory addressed by said first digital value, with the provided correction value being stored at the memory position being addressed; and combining means for digitally combining said first and second digital values and said correction value to provide a digital output value.

Claim 3

The conversion system of claim 1 wherein the system components are controlled to convert a plurality of sequentially sampled analog input values into a plurality of corresponding digital output values.

Claim 4

The conversion system of claim 1 wherein a plurality of correction values are stored into the cells of the memory by a calibration process executed prior to the analog-to-digital operation of the system upon the analog input signal.

Claim 5

The conversion system of claim 1 wherein a plurality of correction values are stored into the cells of the memory by a calibration process executed at periodic times interspaced with the analog-to-digital operation of the system upon the analog input signal.

Claim 6

The conversion system of claim 1 wherein the combining means includes: a linearity correction adder to which the second digital value and the correction value are applied to produce the least significant bits of the digital output value; and a bit overlap adder to which the first digital value and the most significant bit of the linearity correction adder output are applied to produce the most significant bits of the digital output value of the system.

Claim 7

The conversion system of claim 1 wherein the combining means includes: a bit overlap adder to which the first digital value and the most significant bit of the second digital value are applied to produce an intermediate digital output; and a linearity correction adder to which said intermediate digital output, said second digital value, and said correction value are applied to produce the digital output value of the system.

Claim 8

The conversion system of claim 1 wherein the correction means includes a microprocessor and a digital-to-analog converter which generates a calibration signal under control of the microprocessor for application to the input of the conversion system.

Claim 9

The conversion system of claim 1 wherein the correction means includes a microprocessor and a sine wave generator which is controlled by the microprocessor to provide a sine wave input signal to the conversion system.

Claim 10

The conversion system of claim 1 including a multiplex circuit for selectively switching the input of the conversion system between the analog input signal and a signal generated by the correction means.

Claim 11

The conversion system of claim 1 wherein the first converting means includes a sample and hold circuit to which the analog input signal is applied, and an analog-to-digital converter to which is applied the signal held by said sample and hold circuit, said analog-to-digital converter having a bit resolution which is less than the bit resolution of the overall conversion system.

Claim 12

The conversion system of claim 1 wherein the second converting means includes a digital-to-analog converter having a bit resolution which is less than the bit resolution of the overall conversion system.

Claim 13

The conversion system of claim 1 wherein the third converting means includes an analog-to-digital converter having a bit resolution which is less than the bit resolution of the overall conversion system.

Claim 14

The conversion system of claim 1 wherein the correction value stored in the digital memory was derived by executing a conversion by the system of a digitally controlled calibrating input value and measuring the amount of correction needed, when said first digital value is addressing the stored correction value, to make the system digital output value equal to a digital value which controls the calibrated input value.

Claim 15

The conversion system of claim 1 wherein the correction value stored in the digital memory was derived by executing a conversion by the system of a sine wave input signal, performing a fast Fourier transform of the system converted output signal, analyzing the harmonics in the output signal, and determining what value is needed, when said first digital value is addressing the stored correction value, to make the output signal have the lowest harmonic content.

Claim 16

An analog-to-digital conversion system converting an analog input signal into corresponding digital output values, said conversion system comprising: a microprocessor (30); a multiplex circuit (24) for applying either a calibration signal (32, 34) or the analog input signal (26) to the conversion system, said multiplex circuit being under the control of said microprocessor; a sample and hold circuit (22) to which the signal from said multiplex circuit is applied; a first analog-to-digital converter (10) for converting the signal held by said sample and hold circuit to a first digital signal (lD); a first digital-to-analog converter (14) to which said first digital signal is applied; a digital memory (38) addressed by said first digital signal, said memory outputting predetermined correction values (CV); a difference circuit (42, 44, 46) for providing an intermediate analog signal (2IA) which is equal to the difference between the sampled and held input signal and the output (1IA) of said first digital-to-analog converter; a second analog-to-digital converter (20) which converts said intermediate analog signal (2IA) into a second digital signal (2D); and means for combining correction values from the digital memory with the first and second digital signals to provide the system digital output values (50); said correction values being determined, under control of the microprocessor, by applying the calibration signal to the conversion system and noting the correct instantaneous value needed to give the desired output when the first digital signal is addressing the stored correction value.

Claim 17

An analog-to-digital conversion system converting an analog input signal into corresponding digital output values, said conversion system comprising: a microprocessor (30); a multiplex circuit (24) for applying either a calibration signal (32, 34) or the analog input signal (26) to the conversion system, said multiplex circuit being under the control of said microprocessor; a sample and hold circuit (22) to which the signal from said multiplex circuit is applied; a first analog-to-digital converter (10) for converting the signal held by said sample and hold circuit to a first digital signal (lD); a first digital-to-analog converter (14) to which said first digital signal is applied; a digital memory (38) addressed by said first digital signal, said memory outputting predetermined correction values (CV); a difference circuit (42, 44, 46) for providing an intermediate analog signal (2IA) which is equal to the difference between the sampled and held input signal and the output (1IA) of said first digital-to-analog converter; a second analog-to-digital converter (20) which converts said intermediate analog signal (2IA) into a second digital signal (2D); and means for combining correction values from the digital memory with the first and second digital signals to provide the system digital output values (50); said correction values being determined, under control of the microprocessor, by applying the calibration signal to the conversion system and noting the correct instantaneous value needed to give the desired output when the first digital signal is addressing the stored correction value.

Claim 20

The method of claim 18 including the additional steps of: converting a digitally controlled analog calibration signal to a digital output signal; providing an error signal responsive to the difference between the digital output signal and the digital signal which controls the analog calibration signal; and determining the correction values which must be placed into the digital memory to yield the smallest error signal when the addressed values in the memory are combined with the first and second digital signals.