Patent US4901269A successfully refreshed from Google Patents.
US4901269A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple-stage carry-select adder having unique construction for initial adder cells
Assignee: Siemens AG
•
Filing: 1987-08-21
•
Granted: 1990-02-13
•
Expires: 2007-08-21
Abstract
Abstract An adder, operating on the carry-select principle, provides for the transmission of two carry signals (c-0, c-1) and incorporates only one half-added (HA1) for the formation of the sum signal. Every adder stage (AS) of the adder is composed of an initial adder cell (AZA) and of a plurality of normal adder cells (AZN). The initial adder cell (AZA) forms a sum signal (s) from the supplied operand bits (a, b) upon employment of one of the two carry signals (c-0, c-1) and of a selection signal (e), which signals are permanently set. The normal adder cells (AZN) generate a sum signal from the operand bits supplied to them upon employment of one of two carry signals selected by the selection signal (e) supplied from the next-lower adder cell. The initial adder cell (AZA) and the normal adder cells (ANS) differ in their carry networks (CSA, CSN) which employ Manchester carry chains for the generation or transmission of the two carry signals (c-0, c-1). The adder cells are identically constructed and are particularly suited as basic cells for producing adders, using the CAD method.
Inventors
- 👤 Anton Stoelzle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:42
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/507
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
369 words
An adder for processing n-bit-wide operands (a,b) with the assistance of n/m adder stages, each having a processing width of m-bits for m-bit-wide sub-operands, each adder stage comprising in combination: (a) an initial adder coil (AZA) for the least significant bit of a sub-operand and m-1 normal adder cells (AZN), constructed alike, one each for the remaining bits of the sub-operand; (b) each adder cell (AZA, AZN) being connected to receive a first carry-in signal and a second carry-in signal from a next-lower adder cell, to generate a sum signal (S) from the operand bits supplied to it and from one of said carry-in signals, and to generate a first carry-out signal and a second carry-out signal, said carry-out signals are supplied to a next adder cell of this stage or the initial adder cell of the next higher adder stage as said carry-in signals; (c) said initial adder cell having means for generating said sum signal by selecting one of said carry-in signals supplied to it in response to a first selection signal, said carry-in signals are permanently set to logic 0 at the least significant adder stage, otherwise the carry signals are supplied from the next-lower stage, for generating a second selection signal for the next higher adder stage by transferring from said initial adder cell to the next higher adder stage, the carry-in signal which is used to generate the sum signal, for generating a first carry-out signal by an AND operation from the operand bits supplied to it and a second carry-out signal by an OR-operation of said operand bits; (d) each normal adder cell (AZN) having means for generating said sum signal by selecting one of said carry-in signals supplied to it in response to said second selection signal, for generating carry-out signals which are identical to said received carry-in signals when the supplied operand bits have different logic values, which are logic 0 when both operand bits are logic 0 and which are logic 1 when both operand bits are logic 1, for transferring the second selection signal to the next adder cell of said stage or to the initial adder cell of the next higher adder stage as said first selection signal.
Claim 2
Dependent Claim
369 words
An adder for processing n-bit-wide operands (a,b) with the assistance of n/m adder stages, each having a processing width of m-bits for m-bit-wide sub-operands, each adder stage comprising in combination: (a) an initial adder coil (AZA) for the least significant bit of a sub-operand and m-1 normal adder cells (AZN), constructed alike, one each for the remaining bits of the sub-operand; (b) each adder cell (AZA, AZN) being connected to receive a first carry-in signal and a second carry-in signal from a next-lower adder cell, to generate a sum signal (S) from the operand bits supplied to it and from one of said carry-in signals, and to generate a first carry-out signal and a second carry-out signal, said carry-out signals are supplied to a next adder cell of this stage or the initial adder cell of the next higher adder stage as said carry-in signals; (c) said initial adder cell having means for generating said sum signal by selecting one of said carry-in signals supplied to it in response to a first selection signal, said carry-in signals are permanently set to logic 0 at the least significant adder stage, otherwise the carry signals are supplied from the next-lower stage, for generating a second selection signal for the next higher adder stage by transferring from said initial adder cell to the next higher adder stage, the carry-in signal which is used to generate the sum signal, for generating a first carry-out signal by an AND operation from the operand bits supplied to it and a second carry-out signal by an OR-operation of said operand bits; (d) each normal adder cell (AZN) having means for generating said sum signal by selecting one of said carry-in signals supplied to it in response to said second selection signal, for generating carry-out signals which are identical to said received carry-in signals when the supplied operand bits have different logic values, which are logic 0 when both operand bits are logic 0 and which are logic 1 when both operand bits are logic 1, for transferring the second selection signal to the next adder cell of said stage or to the initial adder cell of the next higher adder stage as said first selection signal.
Claim 3
Dependent Claim
121 words
The adder according to claim 1, wherein each of said adder cells (AZN, AZA) comprises: a first half-adder (HA1) which carries out an exclusive-OR operation of the supplied operand bits (a i , b i ) and manifests the result of said exclusive-OR operation in inverted (pn) and non-inverted (p) form; a multiplexer circuit (MUX) which connects one of the carry-in signals (c-0, c-1) through to the multiplexer output dependent on a selection signal (e); a second half-adder (HA2) which connects the result (p, pn) through to an adder cell output as a sum signal (s), dependent on the multiplexer output signal; and a carry network (CSA, CSN) which generates the two carry-out signals (c-0, c-1) for the next-higher adder cell.
Claim 4
Dependent Claim
108 words
The adder according to claim 2, wherein said first half-adder comprises: a first NAND element (NA1) and a first NOR element (NO1) each connected to receive the operand bits (a i , b i ) to be operated; a second NOR element (NO2) which is connected to the output of the first NOR element (NO1) a first inverter element (V1) connected to the output of the first NAND element (NA1), and said second NOR element generates the result (p); and a second inverter element (V2) which is connected to the output of the second NOR element (NO2) and which generates the operation result (p) in inverted form (pn).
Claim 5
Dependent Claim
82 words
The adder according to claim 2 or 3, wherein said second half-adder (HA2) comprises: a first transistor (TR1) controlled by the multiplexer output and arranged between the second NOR element (NO2) of the first half-adder and the input of a third inverter (V5); and a transistor (TR2) complementary to the first transistor (TR1) controlled by the multiplier output and arranged between the output of the second inverter element (V2) of the first half-adder and the input of the third inverter element (V5).
Claim 6
Dependent Claim
74 words
The adder according to claim 2, wherein said carry network (CSA) comprises a fourth inverter element (V4) which is connected to the output of the first NOR element (NO1) of the first half-adder, and at whose output one of said two carry-out signals (c-1) for the next adder cell is output, the other of said two carry-out signals (c-0) being taken at the output of the first inverter element (V1) of the first-half adder.
Claim 7
Dependent Claim
191 words
The adder comprising to claim 2, wherein said carry network comprises: a first transistor pair (TG1) of complementary transistors connected in parallel which transmits a first carry-out signal (c-0) from the preceding adder cell to the next adjacent one, and a second transistor pair (TG2) of complementary transistors connected in parallel which transmits a second carry-out signal (c-1) from the preceding adder cell to the next, whereby one transistor of each transistor pair (TG1), (TG2) is controlled by the result (p) and the other transistor of each transistor pair is controlled by the inverter result (pn) of the first half-adder; two transistors (TR3, TR4) of a first conductivity type whose control input is connected to the output of the first NOR element (NO1) of the first half-adder and whose current conductive path is connected between a fixed potential (VP1) corresponding to binary 0 and said carry-out signals; and two transistors of a second conductivity type (TR5, TR6) whose control input is connected to the output of the first NAND element (NA1) and whose current conductive path is connected between a fixed potential (VP2) corresponding to binary 1 and said carry-out signals.
Claim 8
Dependent Claim
88 words
The adder according to one of the claim 2, 3 or 4, wherein said multiplexer circuit (MUX) comprises: a second NAND element (NA2) to which the one carry-in signal (c-0), and the selection signal (e) through an inverter, is supplied; a third NAND element (NA3) to which the other carry-in signal (c-1) is supplied and to which the selection signal (e) is directly supplied; a fourth NAND element (NA4) which is connected to the outputs of the second and third NAND elements and which forms the multiplexer output.
References Cited (Backward Citations)
US3993891A
Cited
US4525797A
Cited
EP0130397A1
Cited
US4675837A
Cited
EP0164450A2
Cited
US4704701A
Cited
US4623982A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |