EP0164450A2
Expired / Lapsed
EP
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A carry circuit suitable for a high-speed arithmetic operation
Assignee: NEC Corp
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Filing: 1984-12-27
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Granted: —
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Expires: 2004-12-27
Abstract
Abstract @ A carry circuit used in an arithmetic unit, such as an adder, a subtractor, has to process a carry operation for producing a carry signal to be transferred to the following carry operation stage according to a carry signal transferred from the previous carry operation stage. To process carry operation at a high-speed, an improved carry circuit performs two operations before the carry signal from the previous stage is received. One of the operations is processed by using a signal representing that the carry signal from the previous stage is present. The other operation is processed by using another signal representing that the carry signal from the previous stage is absent. These two operations have been terminated when the carry signal from the previous stage is received. The carry signal from the previous stage is used to select either one of results of the two operations. Thus, transmission of a carry signal to the following stage can be performed at a high-speed.
Inventors
- 👤 Kouichi C/O Nec Corp. Yamada
- 👤 Masatoshi C/O Nec Corp. Mizuno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 03:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/507
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
161 words
A carry circuit for performing a carry operation according to a first carry signal from the previous stage and at least one input data and producing a second carry signal to be transferred to the following stage, comprising an input portion for receiving said first carry signal from said previous stage, a first means for generating a first signal which represent presence of said first carry signal, a second means for generating a second signal internally which represents absence of said first carry signal, a third means for processing a carry operation according to said input data and said first signal,a fourth means for processing a carry operation according to said input data and said second signal, a selecting means for selecting either one of outputs of said third and fourth means in accordance with presence or absence of said first carry signal, and an output portion for transferring the selected output as said second carry signal to the following stage.
Claim 2
Dependent Claim
161 words
A carry circuit for performing a carry operation according to a first carry signal from the previous stage and at least one input data and producing a second carry signal to be transferred to the following stage, comprising an input portion for receiving said first carry signal from said previous stage, a first means for generating a first signal which represent presence of said first carry signal, a second means for generating a second signal internally which represents absence of said first carry signal, a third means for processing a carry operation according to said input data and said first signal,a fourth means for processing a carry operation according to said input data and said second signal, a selecting means for selecting either one of outputs of said third and fourth means in accordance with presence or absence of said first carry signal, and an output portion for transferring the selected output as said second carry signal to the following stage.
Claim 3
Dependent Claim
29 words
A carry circuit as claimed in claim 1, in which the output of said third means is selected when said first carry signal is present at said input portion.
Claim 4
Dependent Claim
29 words
A carry circuit as claimed in claim 1, in which the output of said fourth means is selected when said first carry signal is absent at said input portion.
Claim 5
Dependent Claim
31 words
A carry circuit as claimed in claim 1, in which the outputs of said third and fourth means are produced before said first carry signal is received at said input portion.
Claim 6
Dependent Claim
227 words
A carry circuit having a plurality of carry operating stages comprising at least one stage including a first transfer gate and a second transfer gate, a first switching gate and a second switching gate, a first means for applying a first signal to an input end of said first transfer gate before a carry signal from the previous stage is received at a carry input portion, a second means for applying a second signal to an input end of said second transfer gate before said carry signal from said previous stage is received at said carry input portion, means for controlling on and off of saidfirst and second transfer gates according to a SUM signal of two bits to be added, means for applying a CARRY signal produced according to combination of said two bits to be added to input ends of said first and second switching gates, means for coupling output ends of said first and second switching gates to output ends of said first and second transfer gates, respectively, means for controlling on and off of said first and second switching gates according to an inverted signal of said SUM signal, means for selecting either one of outputs of said first and second transfer gates according to said carry signal from said previous stage, and means for transferring the selected output to the following stage.
Claim 7
Dependent Claim
227 words
A carry circuit having a plurality of carry operating stages comprising at least one stage including a first transfer gate and a second transfer gate, a first switching gate and a second switching gate, a first means for applying a first signal to an input end of said first transfer gate before a carry signal from the previous stage is received at a carry input portion, a second means for applying a second signal to an input end of said second transfer gate before said carry signal from said previous stage is received at said carry input portion, means for controlling on and off of saidfirst and second transfer gates according to a SUM signal of two bits to be added, means for applying a CARRY signal produced according to combination of said two bits to be added to input ends of said first and second switching gates, means for coupling output ends of said first and second switching gates to output ends of said first and second transfer gates, respectively, means for controlling on and off of said first and second switching gates according to an inverted signal of said SUM signal, means for selecting either one of outputs of said first and second transfer gates according to said carry signal from said previous stage, and means for transferring the selected output to the following stage.
Claim 8
Dependent Claim
141 words
A carry circuit having at least two blocks in which a first block produces a first carry signal according to data to be arithmetically operated in said first block and a second block coupled to said first block produces a second carry signal according to said first carry signal and data to be arithmetically operated in said second block, said second block comprising a first means for preliminarily producing a first signal to be outputted as said second carry signal when said first carry signal is applied to said second block, a second means for preliminarily producing a second signal to be outputted as said second carry signal when said first carry signal is not applied to said second block, and a selecting means for selecting either one of said first and second signals in accordance with said first carry signal.
Claim 9
Dependent Claim
141 words
A carry circuit having at least two blocks in which a first block produces a first carry signal according to data to be arithmetically operated in said first block and a second block coupled to said first block produces a second carry signal according to said first carry signal and data to be arithmetically operated in said second block, said second block comprising a first means for preliminarily producing a first signal to be outputted as said second carry signal when said first carry signal is applied to said second block, a second means for preliminarily producing a second signal to be outputted as said second carry signal when said first carry signal is not applied to said second block, and a selecting means for selecting either one of said first and second signals in accordance with said first carry signal.
References Cited (Backward Citations)
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