Patent US4901265A successfully refreshed from Google Patents.
US4901265A
Expired / Lapsed
US
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Pseudorandom dither for frequency synthesis noise
Assignee: Qualcomm Inc
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Filing: 1987-12-14
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Granted: 1990-02-13
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Expires: 2007-12-14
Abstract
Abstract A method and apparatus for reducing spurious output noise in digital frequency synthesizers employing sine amplitude converters connected to Digital-to-Analog converters to generate analog waveforms from sine amplitude data. Random or pseudorandom numbers having a value equal to or less than plus or minus one-half of a minimum quantization step or value change for the sine amplitude data are generated and added to the sine amplitude data with the resulting sum being transferred to the Digital-to-Analog converter. In one embodiment, a summation circuit is connected between an output of the sine function converter and an input of the Digital-to-Analog converter and also has a second input connected to a pseudorandom number generator which provides Pseudorandom numbers varying in value over a range of ±1/2 n+1 times a least significant step value, or bit for base 2, of a corresponding Digital-to-Analog input data value where n is greater than or equal to 1.
Inventors
- 👤 Richard J. Kerr
- 👤 Lindsay A. Weaver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:17
CPC Classifications
G; G06; G06J; G06J1/00; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328; G06F2101/00; G06F2101/04; G06F2211/00; G06F2211/902
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
103 words
A method of reducing spurious response output from a digital frequency synthesizer where the synthesizer employs a phase angle accumulator connected to a sine function converter to convert phase angle data to digital sine amplitude numbers, and with an output of the sine converter connected to a Digital-to-Analog converter to generate an analog signal in response to the since amplitude numbers, comprising the steps of: providing a sequence of pseudorandomly varying numbers; adding one of said pseudorandomly varying numbers to each of said sine amplitude numbers output by said sine function converter; and truncating a resulting sum before input to said Digital-to-Analog converter.
Claim 2
Independent Claim
103 words
A method of reducing spurious response output from a digital frequency synthesizer where the synthesizer employs a phase angle accumulator connected to a sine function converter to convert phase angle data to digital sine amplitude numbers, and with an output of the sine converter connected to a Digital-to-Analog converter to generate an analog signal in response to the since amplitude numbers, comprising the steps of: providing a sequence of pseudorandomly varying numbers; adding one of said pseudorandomly varying numbers to each of said sine amplitude numbers output by said sine function converter; and truncating a resulting sum before input to said Digital-to-Analog converter.
Claim 3
Dependent Claim
24 words
The method of claim 1 wherein the step of providing further comprises the step of scaling said pseudorandomly varying numbers to a predetermined magnitude.
Claim 4
Dependent Claim
51 words
The method of claim 1 wherein the Digital-to-Analog converter uses a pre-selected minimum quantization step for input data and the step of providing psuedorandom numbers further comprises the step of: generating pseudorandomly varying numbers having magnitudes equal to or between ±1/2 the minimum quantization step of the Digital-to-Analog converter input numbers.
Claim 5
Dependent Claim
51 words
The method of claim 3 wherein the pseudorandom and sine amplitude numbers each comprise digital words n and k bits wide respectively and the step of adding comprises adding said pseudorandom number bits to said sine amplitude bits beginning at ±1/2 a least significant bit value of the Digital-to-Analog converter resolution.
Claim 6
Dependent Claim
42 words
The method of claim 4 wherein the step of generating further comprises the step of providing pseudorandom numbers having a value in the range of ±1/2 n times said least significant bit value where n is greater than or equal to 1.
Claim 7
Independent Claim
130 words
An apparatus for reducing spurious output response in a direct digital frequency synthesizer, employing a phase angle accumulator connected to a sine function converter to convert phase data to digital amplitude numbers and being further connected to a Digital-to-Analog converter which generates an analog signal according to the amplitude numbers, comprising: a pseudorandom number generator; scaler means for receiving generated pseudorandom numbers and for scaling a magnitude of said pseudorandom numbers by a predetermined amount; and summation means for adding together two numbers to generate a sum, having a first input connected to an output of said sine function converter, a second input connected to said sine function converter, a second input connected to an output of said scaler, and an output connected to the input of said Digital-to-Analog converter.
Claim 8
Independent Claim
130 words
An apparatus for reducing spurious output response in a direct digital frequency synthesizer, employing a phase angle accumulator connected to a sine function converter to convert phase data to digital amplitude numbers and being further connected to a Digital-to-Analog converter which generates an analog signal according to the amplitude numbers, comprising: a pseudorandom number generator; scaler means for receiving generated pseudorandom numbers and for scaling a magnitude of said pseudorandom numbers by a predetermined amount; and summation means for adding together two numbers to generate a sum, having a first input connected to an output of said sine function converter, a second input connected to said sine function converter, a second input connected to an output of said scaler, and an output connected to the input of said Digital-to-Analog converter.
Claim 9
Dependent Claim
28 words
The apparatus of claim 6 further comprising truncation means connected between said summation means output and said Digital-to-Analog converter input for truncating said sum to a predetermined resolution.
Claim 10
Dependent Claim
30 words
The apparatus of claim 7 wherein said truncation means has an output with a bit width equal to or less than a predetermined resolution bit width of said Digital-to-Analog converter.
Claim 11
Dependent Claim
28 words
The apparatus of claim 6 wherein said pseudorandom number generator produces numbers having magnitudes equal to or between ±1/2 a pre-selected minimum quantization step of said Digital-to-Analog converter.
Claim 12
Dependent Claim
64 words
The apparatus of claim 9 wherein each sine amplitude number comprises digital words k bits wide and said pseudorandom number source comprises bit generation means for producing numbers in the form of digital words n bits wide and said summation means adds said pseudorandom number words to said sine amplitude words beginning at ±1/2 a least significant bit value of the Digital-to-Analog converter resolution.
Claim 13
Dependent Claim
38 words
The apparatus of claim 10 wherein said bit generation means produces pseudorandomly varying numbers having a value in the range of ±1/2 n times said least significant bit value where n is greater than or equal to 1.
Claim 14
Independent Claim
96 words
A method of reducing spurious response from a digital frequency synthesizer where the synthesizer employs a phase angle accumulator connected to a sine function converter to convert phase angle data to digital sine amplitude numbers, and with an output of the sine converter connected to a Digital-to-Analog converter which generates an analog signal in response to the sine amplitude numbers, comprising the steps of: providing a sequence of randomly varying numbers; adding one of said randomly varying numbers to each of said sine amplitude numbers; and truncating a resulting sum before input to said Digital-to-Analog converter.
Claim 15
Independent Claim
96 words
A method of reducing spurious response from a digital frequency synthesizer where the synthesizer employs a phase angle accumulator connected to a sine function converter to convert phase angle data to digital sine amplitude numbers, and with an output of the sine converter connected to a Digital-to-Analog converter which generates an analog signal in response to the sine amplitude numbers, comprising the steps of: providing a sequence of randomly varying numbers; adding one of said randomly varying numbers to each of said sine amplitude numbers; and truncating a resulting sum before input to said Digital-to-Analog converter.
Claim 16
Dependent Claim
18 words
The method of claim 12 further comprising the step of scaling said random numbers to a predetermined magnitude.
Claim 17
Dependent Claim
38 words
The method of claim 12 wherein the step of providing random numbers further comprises the step of: generating randomly varying numbers having magnitudes equal to or between ±1/2 the minimum quantization step of the Digital-to-Analog converter input numbers.
Claim 18
Dependent Claim
53 words
The method of claim 14 wherein the generated random and sine amplitude numbers each comprise digital data words n and k bits wide respectively and the step of adding comprises adding said random number bits to said sine amplitude bits beginning at ±1/2 a least significant bit value of the Digital-to-Analog converter resolution.
Claim 19
Dependent Claim
44 words
The method of claim 15 wherein the step of generating randomly varying numbers further comprises the step of providing random numbers having a value in the range of ±κn times said least significant bit value where n is greater than or equal to 1.
Claim 20
Independent Claim
134 words
An apparatus for reducing spurious output response in a direct digital frequency synthesizer, employing a phase angle accumulator connected to a sine function converter to convert phase data to digital amplitude numbers and being further connected to a Digital-to-Analog converter which generates an analog signal according to the amplitude numbers, comprising: summation means for adding together two or more numbers to generate a sum, having a first input connected to an output of said sine function converter and an output connected to the input to said Digital-to-Analog converter; a random number generator connected to a second input of said summation circuit; and scaler means connected between said summation means second input and said random number generator for receiving generated random numbers and for scaling a magnitude of said random numbers by a predetermined amount.
Claim 21
Independent Claim
134 words
An apparatus for reducing spurious output response in a direct digital frequency synthesizer, employing a phase angle accumulator connected to a sine function converter to convert phase data to digital amplitude numbers and being further connected to a Digital-to-Analog converter which generates an analog signal according to the amplitude numbers, comprising: summation means for adding together two or more numbers to generate a sum, having a first input connected to an output of said sine function converter and an output connected to the input to said Digital-to-Analog converter; a random number generator connected to a second input of said summation circuit; and scaler means connected between said summation means second input and said random number generator for receiving generated random numbers and for scaling a magnitude of said random numbers by a predetermined amount.
Claim 22
Dependent Claim
28 words
The apparatus of claim 17 further comprising truncation means connected between said summation means output and said Digital-to-Analog converter input for truncating said sum to a predetermined resolution.
Claim 23
Dependent Claim
28 words
The apparatus of claim 17 wherein said random number generator produces numbers having magnitudes equal to or between ±1/2 a pre-selected minimum quantization step of said Digital-to-Analog converter.
Claim 24
Dependent Claim
64 words
The apparatus of claim 19 wherein each sine amplitude number comprises digital words k bits wide and said random number source comprises bit generation means for producing numbers in the form of digital words n bits wide and said summation means adds said random number words to said sine amplitude words beginning at ±1/2 a least significant bit position of the Digital-to-Analog converter resolution.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |