US4901128A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1986-11-24
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Granted: 1990-02-13
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Expires: 2006-11-24
Abstract
Abstract A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
Inventors
- 👤 Hideo Sunami
- 👤 Tokuo Kure
- 👤 Masanobu Miyao
- 👤 Yoshifumi Kawamoto
- 👤 Katsuhiro Shimohigashi
- 👤 Yoshio Sakai
- 👤 Osamu Minato
- 👤 Toshiaki Masuhara
- 👤 Mitsumasa Koyanagi
- 👤 Shinji Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/39; H10B12/395; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
265 words
A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a semiconductor surface region having a first conductivity type, wherein said insulated-gate field-effect transistor comprises: a gate electrode electrically connected to one of the plurality of word lines, a source and drain provided in the semiconductor surface region, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, and a gate insulation film provided between the semiconductor surface region and the gate electrode, the gate insulation film being formed less than 50 nm; and wherein said capacitor comprises: a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 1 μm, wherein the depth of the groove is greater than a distance between inner walls of the grooves, and wherein the semiconductor surface region surrounding the groove acts as a first electrode, a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a composite film of SiO 2 and Si 3 N 4 , and a second electrode formed in the groove over the capacitor insulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein the second electrode comprises a polycrystalline silicon, and wherein the groove is filled with the second electrode, wherein an individual groove is provided for forming the capacitor for each memory cell.
Claim 2
Dependent Claim
265 words
A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a semiconductor surface region having a first conductivity type, wherein said insulated-gate field-effect transistor comprises: a gate electrode electrically connected to one of the plurality of word lines, a source and drain provided in the semiconductor surface region, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, and a gate insulation film provided between the semiconductor surface region and the gate electrode, the gate insulation film being formed less than 50 nm; and wherein said capacitor comprises: a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 1 μm, wherein the depth of the groove is greater than a distance between inner walls of the grooves, and wherein the semiconductor surface region surrounding the groove acts as a first electrode, a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a composite film of SiO 2 and Si 3 N 4 , and a second electrode formed in the groove over the capacitor insulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein the second electrode comprises a polycrystalline silicon, and wherein the groove is filled with the second electrode, wherein an individual groove is provided for forming the capacitor for each memory cell.
Claim 3
Dependent Claim
40 words
A semiconductor memory according to claim 1, wherein the first electrode comprises an impurity region formed into the semiconductor surface region, and wherein an impurity concentration of the region is higher than an impurity concentration of the semiconductor surface region.
Claim 4
Dependent Claim
23 words
A semiconductor memory according to claim 1, wherein said first conductivity is n-type, and wherein the first electrode is set at ground potential.
Claim 5
Dependent Claim
38 words
A semiconductor memory according to claim 2, wherein the impurity region is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and wherein the depth of the groove is more than 2 μm.
Claim 6
Dependent Claim
25 words
A semiconductor memory according to claim 1, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten.
Claim 7
Dependent Claim
35 words
A semiconductor memory according to claim 1, wherein the plurality of word lines comprises at least one material elected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, and the plurality of bit lines comprises Al.
Claim 8
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein the plurality of memory cells is arranged as a folded-bit line construction.
Claim 9
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein the plurality of memory cells is arranged as an open-bit line construction.
Claim 10
Dependent Claim
32 words
A semiconductor memory according to claim 1, wherein the drain or source of the insulated-gate field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells.
Claim 11
Dependent Claim
296 words
A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor, wherein said insulated-gate field-effect transistor comprises: a gate electrode electrically connected to one of the plurality of word lines, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, a source and drain provided in a semiconductor surface region having first conductivity type, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, wherein the drain or source of the insulated-gate field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and a gate insulation film provided between the semiconductor surface region and the gate electrode, the gate insulation film being formed less than 50 nm; and wherein said capacitor comprises: a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 1 μm, wherein the depth of the groove is greater than a distance between inner walls of the groove, and wherein the semiconductor surface region surrounding the groove acts as a first electrode, a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a composite film of SiO 2 and Si 3 N 4 , and a second electrode formed in the groove over the capacitor insulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein the second electrode comprises a polycrystalline silicon, and wherein the groove is filled with the second electrode, wherein an individual groove is provided for forming the capacitor for each memory cell.
Claim 12
Dependent Claim
296 words
A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor, wherein said insulated-gate field-effect transistor comprises: a gate electrode electrically connected to one of the plurality of word lines, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, a source and drain provided in a semiconductor surface region having first conductivity type, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, wherein the drain or source of the insulated-gate field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and a gate insulation film provided between the semiconductor surface region and the gate electrode, the gate insulation film being formed less than 50 nm; and wherein said capacitor comprises: a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 1 μm, wherein the depth of the groove is greater than a distance between inner walls of the groove, and wherein the semiconductor surface region surrounding the groove acts as a first electrode, a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a composite film of SiO 2 and Si 3 N 4 , and a second electrode formed in the groove over the capacitor insulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein the second electrode comprises a polycrystalline silicon, and wherein the groove is filled with the second electrode, wherein an individual groove is provided for forming the capacitor for each memory cell.
Claim 13
Dependent Claim
40 words
A semiconductor memory according to claim 10, wherein the first electrode comprises an impurity region formed into the semiconductor surface region, and wherein an impurity concentration of the region is higher than an impurity concentration of the semiconductor surface region.
Claim 14
Dependent Claim
35 words
A semiconductor memory according to claim 10, wherein the plurality of word lines comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, and the plurality of bit lines comprises Al.
Claim 15
Dependent Claim
23 words
A semiconductor memory according to claim 10, wherein said first conductivity is n-type, and wherein the first electrode is set at ground potential.
Claim 16
Dependent Claim
38 words
A semiconductor memory according to claim 11, wherein the impurity region is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and wherein the depth of the groove is more than 2 μm.
Claim 17
Dependent Claim
20 words
A semiconductor memory according to claim 10, wherein the plurality of memory cells is arranged as a folded-bit line construction.
Claim 18
Dependent Claim
20 words
A semiconductor memory according to claim 10, wherein the plurality of memory cells is arranged as an open-bit line construction.
Claim 19
Dependent Claim
304 words
A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor, wherein said insulated-gate field-effect transistor comprises: a gate electrode electrically connected to one of the plurality of word lines, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, a source and drain provided in a semiconductor surface region having a first conductivity type, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, wherein the drain or source of the insulated-gate and field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and a gate insulation film provided between the semiconductor surface region and the gate electrode; and wherein said capacitor comprises: a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 2 μm, the depth of the groove is greater than a distance between inner walls of the groove, and the semiconductor surface region surrounding the groove acts as a first electrode, wherein the first electrode comprises an impurity region formed into the semiconductor surface region, wherein the region is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a three-layer composite film of SiO 2 , Si 3 N 4 , SiO 2 , and a second electrode formed in the groove over the capacitor inulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein an individual groove is provided for forming the capacitor for each memory cell.
Claim 20
Dependent Claim
304 words
A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor, wherein said insulated-gate field-effect transistor comprises: a gate electrode electrically connected to one of the plurality of word lines, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, a source and drain provided in a semiconductor surface region having a first conductivity type, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, wherein the drain or source of the insulated-gate and field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and a gate insulation film provided between the semiconductor surface region and the gate electrode; and wherein said capacitor comprises: a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 2 μm, the depth of the groove is greater than a distance between inner walls of the groove, and the semiconductor surface region surrounding the groove acts as a first electrode, wherein the first electrode comprises an impurity region formed into the semiconductor surface region, wherein the region is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a three-layer composite film of SiO 2 , Si 3 N 4 , SiO 2 , and a second electrode formed in the groove over the capacitor inulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein an individual groove is provided for forming the capacitor for each memory cell.
Claim 21
Dependent Claim
35 words
A semiconductor memory according to claim 17, wherein the plurality of word lines comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten, and the plurality of bit lines comprises Al.
Claim 22
Dependent Claim
23 words
A semiconductor memory according to claim 17, wherein said first conductivity is n-type, and wherein the first electrode is set at ground potential.
Claim 23
Dependent Claim
20 words
A semiconductor memory according to claim 17, wherein the plurality of memory cells is arranged as a folded-bit line construction.
Claim 24
Dependent Claim
20 words
A semiconductor memory according to claim 17, wherein the plurality of memory cells is arranged as an open-bit line construction.
References Cited (Backward Citations)
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