US4901121A
Expired / Lapsed
US
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Semiconductor device comprising a perforated metal silicide layer
Assignee: AMERICAN TELEPHONE and TELEGRAPH Co AT&T BELL LABS
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Filing: 1988-04-18
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Granted: 1990-02-13
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Expires: 2008-04-18
Abstract
Abstract A method for producing, without etching, a perforated layer of epitaxial metal silicide, especially CoSi 2 , on a single crystal Si substrate, with epitaxial Si overlying the silicide layer. The layer thickness, and the number and size of the openings in the layer are such as to make the structure suitable as an electronic device, in particular, as a permeable base transistor. The number and/or size of the openings is a function of processing parameters such as the substrate orientation, the annealing temperature of the film, or the Co/Si ratio of the deposited material. A device comprising a perforated silicide layer is also disclosed.
Inventors
- 👤 John M. Gibson
- 👤 John C. Hensel
- 👤 Anthony F. Levi
- 👤 Raymond T. Tung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/202; H10D30/01; H10D30/012; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D48/362; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/32; H10P14/3202; H10P14/3241; H10P14/3242; H10P14/3256; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3438; H10P14/3441; H10P14/3442; Y; Y10; Y10S; Y10S148/00; Y10S148/142; Y10S148/147
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
231 words
A transistor comprising (a) a single crystal substrate comprising doped Si, the substrate having a major surface having an orientation with respect to the substrate crystal lattice; (b) a layer of metal silicide in contact with the major surface of the substrate and forming a junction therewith, associated with the junction being a zero bias depletion width W, the thickness of the silicide layer being between about 5% and about 50% of W, the silicide layer having been formed by a process that comprises deposition of metal, or of metal and silicon, or of metal followed by silicon, onto the major surface of the substrate, and annealing of the deposit; (c) a layer of silicon overlying at least a part of the silicide layer, the layer of silicon comprising doped silicon; (d) means for making electrical contact to the substrate, the silicide layer and the layer of silicon, respectively; characterized in that (e) the silicide layer is perforated by a multiplicity of apertures, with silicon, or doped silicon, extending through at least some of the apertures, associated with each aperture being an effective diameter of the aperture, with the average of the effective diameter of the apertures being in the range from about 10% to about 100% of W, with the apertures in the silicide layer having been formed during formation of the silicide layer without use of lithography and/or etching.
Claim 2
Dependent Claim
231 words
A transistor comprising (a) a single crystal substrate comprising doped Si, the substrate having a major surface having an orientation with respect to the substrate crystal lattice; (b) a layer of metal silicide in contact with the major surface of the substrate and forming a junction therewith, associated with the junction being a zero bias depletion width W, the thickness of the silicide layer being between about 5% and about 50% of W, the silicide layer having been formed by a process that comprises deposition of metal, or of metal and silicon, or of metal followed by silicon, onto the major surface of the substrate, and annealing of the deposit; (c) a layer of silicon overlying at least a part of the silicide layer, the layer of silicon comprising doped silicon; (d) means for making electrical contact to the substrate, the silicide layer and the layer of silicon, respectively; characterized in that (e) the silicide layer is perforated by a multiplicity of apertures, with silicon, or doped silicon, extending through at least some of the apertures, associated with each aperture being an effective diameter of the aperture, with the average of the effective diameter of the apertures being in the range from about 10% to about 100% of W, with the apertures in the silicide layer having been formed during formation of the silicide layer without use of lithography and/or etching.
Claim 3
Dependent Claim
37 words
Transistor of claim 1, wherein an electron means free path is associated with the silicide layer, the electron mean free path at 25° C. in the silicide layer being greater than the thickness of the silicide layer.
Claim 4
Dependent Claim
25 words
Transistor of claim 1, wherein the major surface of the substrate forms an angle θ with a (111) lattice plane of the substrate, with θ≲6°.
Claim 5
Dependent Claim
21 words
Transistor of claim 1, wherein the device is associated with at least one other electronic device on a common silicon body.
Claim 6
Dependent Claim
18 words
Transistor of claim 1, wherein the metal is chosen from the group consisting of Co, Ni, and Pd.
Claim 7
Dependent Claim
9 words
Transistor of claim 5, wherein the metal is Co.
Claim 8
Dependent Claim
233 words
Method of fabricating a transistor comprising (a) providing a single crystal Si substrate comprising doped silicon and a major surface; (b) forming on at least a part of the major surface a metal silicide layer, the substrate with the silicide layer thereon forming a junction, associated with the junction being a zero bias depletion width W, the silicide layer thickness being between about 5% and about 50% of W, at least substantial part of the silicide layer being epitaxial with the substrate, the silicide layer formed by a process that comprises deposition of metal, or of metal and silicon, or of metal followed by silicon, onto the major surface of the substrate, and annealing of the deposit; (c) forming a layer of silicon on at least a part of the silicide layer, the silicon layer comprising doped Si; and (d) providing means for electrically contacting the substrate, the silicide layer, and the silicon layer, respectively; characterized in that (e) the silicide layer is perforated silicide layer comprising a multiplicity of apertures, with silicon, or doped silicon, extending through at least some of the apertures, associated with each aperture being an effective diameter of the aperture, with the average of the effective diameter of the apertures being in the range from about 10% to about 100% of W, the apertures in the silicide layer formed during step (b) without use of lithography and/or etching.
Claim 9
Dependent Claim
233 words
Method of fabricating a transistor comprising (a) providing a single crystal Si substrate comprising doped silicon and a major surface; (b) forming on at least a part of the major surface a metal silicide layer, the substrate with the silicide layer thereon forming a junction, associated with the junction being a zero bias depletion width W, the silicide layer thickness being between about 5% and about 50% of W, at least substantial part of the silicide layer being epitaxial with the substrate, the silicide layer formed by a process that comprises deposition of metal, or of metal and silicon, or of metal followed by silicon, onto the major surface of the substrate, and annealing of the deposit; (c) forming a layer of silicon on at least a part of the silicide layer, the silicon layer comprising doped Si; and (d) providing means for electrically contacting the substrate, the silicide layer, and the silicon layer, respectively; characterized in that (e) the silicide layer is perforated silicide layer comprising a multiplicity of apertures, with silicon, or doped silicon, extending through at least some of the apertures, associated with each aperture being an effective diameter of the aperture, with the average of the effective diameter of the apertures being in the range from about 10% to about 100% of W, the apertures in the silicide layer formed during step (b) without use of lithography and/or etching.
Claim 10
Dependent Claim
69 words
Method of claim 7, wherein forming the silicide layer comprises depositing a metal selected from the group consisting of Co, Ni, and Pd, or of the metal and Si, or of the metal followed by Si, onto the major surface of the substrate, and maintaining the substrate at a temperature in the range from about 500° to about 800° C. for a time effective for producing the silicide layer.
Claim 11
Dependent Claim
26 words
Device of claim 7, wherein the orientation of the major surface of the substrate is within about 6° of a (111) lattice plane of the substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |