Patent US4901033A successfully refreshed from Google Patents.
US4901033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency synthesizer with dynamically programmable frequency range of selected loop bandwith
Assignee: NXP USA Inc
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Filing: 1989-05-01
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Granted: 1990-02-13
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Expires: 2009-05-01
Abstract
Abstract A frequency synthesizer which includes at least one phase lock loop operative in a selected loop bandwidth state includes a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state. In another aspect, the frequency synthesizer may include a plurality of phase lock loop circuits; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to the plurality of phase lock loop circuits for setting a common frequency range for the loop bandwidth states of all of the phase lock loop circuits. In still another aspect, the frequency synthesizer includes a phase lock loop circuit; and a bias circuit programmably operative to generate at least one bias signal which is coupled to the phase lock loop circuit for setting a reference frequency range of the loop bandwidth states thereof, the phase lock loop circuit being dynamically programmable to vary the frequency range settings of the loop bandwidth states in relation to the reference frequency range set by the bias circuit.
Inventors
- 👤 Barry W. Herold
- 👤 Omid Tahernia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:57
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/22; H03L7/23; H03L7/08; H03L7/10; H03L7/107; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0898
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
263 words
A frequency synthesizer governed by a frequency channel setting to generate a synthesized frequency signal, said frequency synthesizer including a phase lock loop (PLL) circuit operative in a first loop bandwidth state to maintain said synthesized frequency signal substantially at said frequency channel setting, said PLL circuit programmably settable randomly between old and new frequency channel settings, said PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge the synthesized frequency signal to said new frequency channel setting, said PLL circuit comprising: phase detecting means governed by a reference frequency signal and a feedback frequency signal to generate at least one control signal based on the phase difference between said reference and feedback frequency signals; storage means for maintaining a governing signal; oscillator means controlled by said governing signal to generate said synthesized frequency signal proportional in frequency to the amplitude of said governing signal; means for frequency dividing said synthesized frequency signal in accordance with a programmably settable frequency channel setting to generate said feedback frequency signal; means governed by said at least one control signal to adjust the governing signal of said storage means in a selected one of a plurality of loop bandwidth states including said first and second loop bandwidth states, said adjusting means including a digitally programmable control circuit for dynamically setting the frequency range of the selected loop bandwidth state in one of a predetermined plurality of frequency ranges, whereby an appropriate loop bandwidth frequency range may be dynamically set in accordance with a new frequency channel setting.
Claim 2
Dependent Claim
263 words
A frequency synthesizer governed by a frequency channel setting to generate a synthesized frequency signal, said frequency synthesizer including a phase lock loop (PLL) circuit operative in a first loop bandwidth state to maintain said synthesized frequency signal substantially at said frequency channel setting, said PLL circuit programmably settable randomly between old and new frequency channel settings, said PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge the synthesized frequency signal to said new frequency channel setting, said PLL circuit comprising: phase detecting means governed by a reference frequency signal and a feedback frequency signal to generate at least one control signal based on the phase difference between said reference and feedback frequency signals; storage means for maintaining a governing signal; oscillator means controlled by said governing signal to generate said synthesized frequency signal proportional in frequency to the amplitude of said governing signal; means for frequency dividing said synthesized frequency signal in accordance with a programmably settable frequency channel setting to generate said feedback frequency signal; means governed by said at least one control signal to adjust the governing signal of said storage means in a selected one of a plurality of loop bandwidth states including said first and second loop bandwidth states, said adjusting means including a digitally programmable control circuit for dynamically setting the frequency range of the selected loop bandwidth state in one of a predetermined plurality of frequency ranges, whereby an appropriate loop bandwidth frequency range may be dynamically set in accordance with a new frequency channel setting.
Claim 3
Dependent Claim
173 words
The frequency synthesizer in accordance with claim 1 wherein the storage means includes a capacitive element for maintaining a governing voltage potential thereacross; wherein the adjusting means includes first means selectable for sourcing and sinking current to and from said capacitive element at a first current level for adjusting the voltage thereacross as governed by the at least one control signal, and second means selectable for sourcing and sinking current to and from said capacitive element at a second current level for adjusting the voltage thereacross as governed by the at least one control signal; said first means being selected for said first loop bandwidth state and said second means being selected for said second loop bandwidth state, said first and second current levels being set by at least one bias reference signal; and wherein the control circuit is digitally programmable to dynamically vary said first and second current levels to one of a predetermined plurality of other current levels corresponding to the predetermined plurality of frequency ranges of the selected loop bandwidth.
Claim 4
Dependent Claim
153 words
The frequency synthesizer in accordance with claim 2 wherein each of the first and second means includes a current mirror circuit comprising a diode section, a current generating section governed by the at least one bias reference signal to generate a bias current through said diode section, and an output section which has a gain relationship with said diode section to effect the sourcing and sinking current at the respective one of the first and second current levels which is a magnification of said respective bias current in accordance with the respective gain relationship; and wherein the control circuit includes a plurality of additional switchable diode sections for each of the current mirror circuits, selected ones of said switchable diode sections made operative by the programmed code of a digital word to vary the first and second current levels of said output sections to a current level corresponding to said programmed digital code.
Claim 5
Dependent Claim
86 words
The frequency synthesizer in accordance with claim 3 wherein the control circuit further includes a storage register for dynamically programming the PLL circuit with a coded digital word, a decoder coupled to said storage register and having a plurality of signal outputs which are coupled respectively to the plurality of switchable diode sections, said decoder operative to decode the dynamically programmed digital word of said storage register and render selected diode sections operative by said corresponding signal outputs in accordance with the decoded programmed digital word.
Claim 6
Dependent Claim
33 words
The frequency synthesizer in accordance with claim 2 including a digitally programmable bias circuit for dynamically setting the at least one bias reference signal to one of a predetermined plurality of amplitude levels.
Claim 7
Dependent Claim
60 words
The frequency synthesizer in accordance with claim 5 wherein the adjusting means includes logic means governed by a battery saving signal having sleep and awake cycles to generate a signal responsive to said sleep and awake cycles; and wherein the bias circuit is rendered active and inactive by said generated signal to set the at least one bias reference signal.
Claim 8
Dependent Claim
138 words
A frequency synthesizer comprising: a plurality of phase lock loop (PLL) circuits, each PLL circuit governed by a respective frequency channel setting to generate a synthesized frequency signal, each PLL circuit operative in a first loop bandwidth state to maintain its synthesized frequency signal substantially at its respective frequency channel setting, each PLL circuit programmably settable randomly between old and new frequency channel settings, each PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge its synthesized frequency signal to said new frequency channel setting; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to said plurality of PLL circuits for setting a common frequency range for the first and second loop bandwidth states of all of the PLL circuits.
Claim 9
Dependent Claim
138 words
A frequency synthesizer comprising: a plurality of phase lock loop (PLL) circuits, each PLL circuit governed by a respective frequency channel setting to generate a synthesized frequency signal, each PLL circuit operative in a first loop bandwidth state to maintain its synthesized frequency signal substantially at its respective frequency channel setting, each PLL circuit programmably settable randomly between old and new frequency channel settings, each PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge its synthesized frequency signal to said new frequency channel setting; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to said plurality of PLL circuits for setting a common frequency range for the first and second loop bandwidth states of all of the PLL circuits.
Claim 10
Dependent Claim
47 words
The frequency synthesizer in accordance with claim 7 wherein each PLL circuit includes a dynamically programmable control circuit for varying individually the frequency range setting for its respective first and second loop bandwidth states in relation to the common frequency range set by the common bias circuit.
Claim 11
Dependent Claim
71 words
The frequency synthesizer in accordance with claim 7 wherein each PLL circuit includes first logic means governed by a battery saving signal having sleep and awake cycles to generate a signal responsive to said sleep and awake cycles; and wherein the common bias circuit includes second logic means governed said signals generated by the PLL circuits to render active and inactive the setting of the at least one bias reference signal.
Claim 12
Dependent Claim
104 words
The frequency synthesizer in accordance with claim 7 wherein the common bias circuit includes a current mirror circuit comprising a diode section, a current generating section biased to generate a bias current through said diode section, an output section which has a gain relationship with said diode section to effect the at least one bias reference signal, and a plurality of switchable diode sections, selected ones of said switchable diode sections made to conduct bias current by the programmed code of a digital word to cause a variation in the amplitude of the at least one bias reference signal effected by said output section.
Claim 13
Dependent Claim
157 words
A frequency synthesizer including: a phase lock loop (PLL) circuit governed by a frequency channel setting to generate a synthesized frequency signal, said PLL circuit operative in a first loop bandwidth state to maintain said synthesized frequency signal substantially at said frequency channel setting said PLL circuit programmably settable randomly between old and new frequency channel settings, said PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge the synthesized frequency signal to said new frequency channel setting; and a bias circuit programmably operative to generate at least one bias signal which is coupled to said PLL circuit for setting a reference frequency range of the first and second loop bandwidth states thereof, said PLL circuit including a dynamically programmable control circuit for varying the frequency range settings of the first and second loop bandwidth states in relation to the reference frequency range set by said bias circuit.
Claim 14
Dependent Claim
157 words
A frequency synthesizer including: a phase lock loop (PLL) circuit governed by a frequency channel setting to generate a synthesized frequency signal, said PLL circuit operative in a first loop bandwidth state to maintain said synthesized frequency signal substantially at said frequency channel setting said PLL circuit programmably settable randomly between old and new frequency channel settings, said PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge the synthesized frequency signal to said new frequency channel setting; and a bias circuit programmably operative to generate at least one bias signal which is coupled to said PLL circuit for setting a reference frequency range of the first and second loop bandwidth states thereof, said PLL circuit including a dynamically programmable control circuit for varying the frequency range settings of the first and second loop bandwidth states in relation to the reference frequency range set by said bias circuit.
Claim 15
Dependent Claim
263 words
The frequency synthesizer in accordance with claim 11 wherein the phase lock loop circuit includes: phase detecting means governed by a reference frequency signal and a feedback frequency signal to generate at least one control signal based on the phase difference between said reference and feedback frequency signals; a capacitive element for maintaining a governing voltage potential thereacross; oscillator means controlled by said governing voltage potential to generate said synthesized frequency signal proportional in frequency to the amplitude of said voltage potential; means for frequency dividing said synthesized frequency signal in accordance with a programmably settable frequency channel setting to generate said feedback frequency signal; adjusting means including first means selectable for sourcing and sinking current to and from said capacitive element at a first current level for adjusting the voltage thereacross as governed by the at least one control signal, and second means selectable for sourcing and sinking current to and from said capacitive element at a second current level for adjusting the voltage thereacross as governed by the at least one control signal, said first means being selected for said first loop bandwidth state and said second means being selected for said second loop bandwidth state, said first and second current levels being set by at least one bias reference signal; and wherein the control circuit is digitally programmable to dynamically vary said first and second current levels to one of a predetermined plurality of lesser current levels corresponding to a predetermined plurality of frequency ranges of the selected loop bandwidth within the reference frequency range set by the bias circuit.
Claim 16
Dependent Claim
154 words
The frequency synthesizer in accordance with claim 12 wherein each of the first and second means includes a current mirror circuit comprising a diode section, a current generating section governed by the at least one bias reference signal to generate a bias current through said diode section, and an output section which has a gain relationship with said diode section to effect the sourcing and sinking current at the respective one of the first and second current levels which is a magnification of said respective bias current in accordance with the respective gain relationship; and wherein the control circuit includes a plurality of additional switchable diode sections for each of the current mirror circuits, selected ones of said switchable diode sections made operative by the programmed code of a digital word to attenuate the first and second current levels of said output sections to a lesser current level corresponding to said programmed digital code.
Claim 17
Dependent Claim
86 words
The frequency synthesizer in accordance with claim 13 wherein the control circuit further includes a storage register for dynamically programming the PLL circuit with a coded digital word, a decoder coupled to said storage register and having a plurality of signal outputs which are coupled respectively to the plurality of switchable diode sections, said decoder operative to decode the dynamically programmed digital word of said storage register ad render selected diode sections operative by said corresponding signal outputs in accordance with the decoded programmed digital word.
Claim 18
Dependent Claim
103 words
The frequency synthesizer in accordance with claim 11 wherein the bias circuit includes a current mirror circuit comprising a diode section, a current generating section biased to generate a bias current through said diode section, an output section which as a gain relationship with said diode section to effect the at least one bias reference signal, and a plurality of switchable diode sections, selected ones of said switchable diode sections made to conduct bias current by the programmed code of a digital word to cause a variation in the amplitude of the at least one bias reference signal effected by said output section.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |