Process for making polysilicon field plate with improved suppression of parasitic transistors

Claim 1

A method of forming an integrated circuit comprising the steps of: preparing a silicon substrate region doped a predetermined manner and containing future active areas and future field areas; etching said substrate to form trenches of a predetermined depth in said future field areas; growing a thin barrier layer of high quality oxide on said substrate above said future active and field areas; forming a plate layer of high conductivity polysilicon above said thin layer of oxide to form a conductive polysilicon plate extending downwardly below the surface of said substrate and insulated from said substrate in said future field areas by said thin layer of oxide and having a substantially planar top surface; etching said plate layer until said barrier layer lying above said future active areas is exposed, whereby the top surface of said barrier layer and said plate layer are substantially planar and said conductive plate is buried below said top surface; growing a gate oxide layer above said active areas; forming FETs in selected locations in said active areas; connecting said polysilicon plate to a potential source terminal having a predetermined magnitude and polarity such that said polysilicon plate can apply a predetermined electric field to said substrate to suppress the formation of parasitic transistors in said future field areas; and connecting said FETS to form an integrated circuit.

Claim 2

A method of forming an integrated circuit comprising the steps of: preparing a silicon substrate region doped a predetermined manner and containing future active areas and future field areas; etching said substrate to form trenches of a predetermined depth in said future field areas; growing a thin barrier layer of high quality oxide on said substrate above said future active and field areas; forming a plate layer of high conductivity polysilicon above said thin layer of oxide to form a conductive polysilicon plate extending downwardly below the surface of said substrate and insulated from said substrate in said future field areas by said thin layer of oxide and having a substantially planar top surface; etching said plate layer until said barrier layer lying above said future active areas is exposed, whereby the top surface of said barrier layer and said plate layer are substantially planar and said conductive plate is buried below said top surface; growing a gate oxide layer above said active areas; forming FETs in selected locations in said active areas; connecting said polysilicon plate to a potential source terminal having a predetermined magnitude and polarity such that said polysilicon plate can apply a predetermined electric field to said substrate to suppress the formation of parasitic transistors in said future field areas; and connecting said FETS to form an integrated circuit.