Semiconductor memory device with an improved multi-bit test mode

Claim 2

A semiconductor memory device comprising a memory cell array constituted by a plurality of memory cell bits each of which storing information, and internal signal generation means which reads and outputs simulataneously the information stored in the plural bit memory cells from said memory cell array, provided with operation modes including: a normal mode, in which the information is read from said internal signal generation means based on an external address; and a test mode, in which the information from said internal signal generation means is received by plural bit unit and a logic value corresponding to said received plural bit information is outputted, said device comprising: logical operation means which receives plural bit memory cell information simulataneously from said internal signal generation means and carries out selectively at least two predetermined logical operations for outputting results from said at least two predetermined logical operations; a first terminal for receiving a logical operation select signal; first selection means for selectivity outputting one of the results of the at least two logical operations carried out by said logical operation means in response to said logical operation select signal; a second terminal for receiving a signal for selecting one of said test mode and said normal mode; and second selection means which passes said first selection means output in said test mode and which passes the memory cell information from said internal signal generation means in said normal mode.

Claim 3

A semiconductor memory device according to claim 1, wherein the plural bit memory cell information to said internal signal generation means is selected by external address signals except at least one external address signal whereby, in said test mode, at least one of the pin terminals receiving said external address signals becomes unnecessary, so that said logical operation selection signal is generated in response to the signal applied through said unnecessary external address input pin terminal.

Claim 4

A semiconductor memory device according to claim 1, wherein said logical operation selection signal comprises a first level which is higher than the operation supply voltage of said semiconductor memory device and a second level which is lower than said first level.

Claim 5

A semiconductor memory device according to claim 3, wherein the output of said first operation means is selected when said logical operation select signal is at said first level and the output of said second operation means is selected when said logical operation select signal is at said second level.

Claim 6

A semiconductor memory device according to claim 3, wherein said first operation means provides trilevel output and said second operation means provides bilevel output.

Claim 7

A semiconductor memory device according to claim 2, wherein said first means selectively connects the external address input terminal which should be unnecessary in said test mode to the address buffer in response to the signal of said second terminal.

Claim 8

A semiconductor memory device comprising a memory cell array formed by a plurality of memory cells for storing information, and internal signal generation means for reading and outputting simulataneously multiple bit information stored respectively in a plurality of memory cells from said memory cell array, said memory device being operative selectively in a normal mode in which information is read from said memory array based on an external address and in a test mode in which information from said internal signal generation means is received in plural bit units and a logic value corresponding to said received plural bit information is outputted, said device comprising: first logical operation means responsive to said internal signal generation means for carrying out a first logical operation on said multiple bit information and for generating a result of said first logical operation; second logical operation means responsive to said internal signal generation means for carrying out a second logical operation on said multiple bit information and for generating a result of said second logical operation; means for receiving a first control signal having a first voltage level which is higher than the operational supply voltage of said semiconductor memory device and a second voltage level that is lower than said first voltage level; first switching means responsive to said first control signal for selecting an output of one of said first and second logical operation means; means for receiving a second control signal for selecting one of said test mode and said normal mode of operation of said memory device; an output terminal; and second switching means responsive to said second control signal selecting said test mode for supplying an output of said first switching means to said output terminal.

Claim 9

A semiconductor memory device comprising a memory cell array formed by a plurality of memory cells for storing information, and internal signal generation means for reading and outputting simulataneously multiple bit information stored respectively in a plurality of memory cells from said memory cell array, said memory device being operative selectively in a normal mode in which information is read from said memory array based on an external address and in a test mode in which information from said internal signal generation means is received in plural bit units and a logic value corresponding to said received plural bit information is outputted, said device comprising: first logical operation means responsive to said internal signal generation means for carrying out a first logical operation on said multiple bit information and for generating a result of said first logical operation; second logical operation means responsive to said internal signal generation means for carrying out a second logical operation on said multiple bit information and for generating a result of said second logical operation; means for receiving a first control signal having a first voltage level which is higher than the operational supply voltage of said semiconductor memory device and a second voltage level that is lower than said first voltage level; first switching means responsive to said first control signal for selecting an output of one of said first and second logical operation means; means for receiving a second control signal for selecting one of said test mode and said normal mode of operation of said memory device; an output terminal; and second switching means responsive to said second control signal selecting said test mode for supplying an output of said first switching means to said output terminal.

Claim 10

A semiconductor memory device as recited in claim 7, wherein said first logical operation means provides a trilevel output and said second logical operation means provides a bilevel output.

Claim 11

A semiconductor memory device as recited in claim 8, wherein said first means for receiving a first control signal and said second means for receiving a second control signal comprise at least a separate input terminal.

Claim 12

A semiconductor memory device as recited in claim 9, wherein said separate input terminal is connected to receive said first control signal, and said first switching means is responsive to said first voltage level of said first control signal higher than the operational supply voltage of said semiconductor memory device by selecting said trilevel output of said first logical operation means, said first switching means otherwise selecting said bilevel output of said second logical operation means.

Claim 13

A semiconductor memory device as recited in claim 9, wherein said first means for receiving a first control signal and said second means for receiving a second control signal comprise first and second terminals, said first terminal receiving said first control signal for switching between trilevel and bilevel operation and said second terminal receiving said second control signal for selection of a test and a normal mode of operation.

Claim 14

A semiconductor memory device as recited in claim 9, wherein said second control signal for selecting one of said test mode and said normal mode of operation of said memory device is generated by means responsive to a timing relationship between a plurality of clock signals used in said semiconductor memory device.

Claim 15

A semiconductor memory device according to claim 1, wherein said logical operation means carries out a first operation for outputting a trilevel output signal identifying the information stored in each of the plural bit memory cells from said memory cell array as having a single first logic value common to all said memory cells, a single second logic value common to all said memory cells, or as not having a common value, and said logical operation means further carries out a second operation for outputting a bilevel output signal identifying the information stored in each of the plural bit memory cells from said memory cell array has having a single logic value common to all said memory cells or as not having a single logic value common to all said memory cells.

Claim 16

A semiconductor memory device as recited in claim 1, further comprising an external output terminal means for outputting read-out data from memory cells in a normal mode of operation and for outputting results of the logical operation in a test mode of operation.

Claim 17

A semiconductor memory device comprising a memory cell array formed by a plurality of memory cells for storing information, and internal signal generation means for reading and outputting simultaneously multiple bit information stored respectively in a plurality of memory cells from said memory cell array, said memory device being operative selectively in a normal mode in which information is read from said memory array based on an external address and in a test mode in which information from said internal signal generation means is received in plural bit units and a logic value corresponding to said received plural bit information is outputted, said device comprising: first logical operation means responsive to said internal signal generation means for carrying out a logical product of said multiple bit information to obtain a first multiple bit output signal; second logical operation means responsive to said first logical operation means for carrying out a logical sum of said first multiple bit output signal to obtain a second multiple bit output signal; means for receiving a control signal selecting a first or second testing mode of operation; an output terminal; and switching means responsive to said control signal for applying said first multiple bit output signal or said second multiple bit output signal, selectively, to said output terminal.

Claim 18

A semiconductor memory device comprising a memory cell array formed by a plurality of memory cells for storing information, and internal signal generation means for reading and outputting simultaneously multiple bit information stored respectively in a plurality of memory cells from said memory cell array, said memory device being operative selectively in a normal mode in which information is read from said memory array based on an external address and in a test mode in which information from said internal signal generation means is received in plural bit units and a logic value corresponding to said received plural bit information is outputted, said device comprising: first logical operation means responsive to said internal signal generation means for carrying out a logical product of said multiple bit information to obtain a first multiple bit output signal; second logical operation means responsive to said first logical operation means for carrying out a logical sum of said first multiple bit output signal to obtain a second multiple bit output signal; means for receiving a control signal selecting a first or second testing mode of operation; an output terminal; and switching means responsive to said control signal for applying said first multiple bit output signal or said second multiple bit output signal, selectively, to said output terminal.