Patent US1258233A successfully refreshed from Google Patents.
Patent US4899203A successfully refreshed from Google Patents.
US4899203A
Expired / Lapsed
US
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Semiconductor memory integrated circuit and process of fabricating the same
Assignee: Lapis Semiconductor Co Ltd
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Filing: 1988-12-05
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Granted: 1990-02-06
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Expires: 2008-12-05
Abstract
Abstract In a semiconductor memory integrated circuit device having a stacked capacitor cell, a first plate electrode and a first dielectric film are formed underneath a charge storage electrode a charge storage electrode, and a second dielectric film and a second plate electrode are formed over the charge storage electrode. The charge storage electrode has contact with the diffusion region through a contact hole penetrating the first dielectric material. The first and second plate electrodes are connected via a contact hole penetrating the first and second electric films outside the cell area. Because both the upper surface and the lower surface of the charge storage electrode are utilized for formation of the capacitor the size of the capacitor can be halved to produce the same capacitance.
Inventors
- 👤 Masayoshi Ino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
208 words
A semiconductor memory integrated circuit device having a stacked capacitor cell comprising: (a) a semiconductor substrate; (b) a first diffusion region, a channel region and a second diffusion region formed in the substrate; (c) a gate insulating film and a gate electrode formed over the channel region; (d) a first insulating film formed over said second diffusion region; (e) a first plate electrode formed over said first insulating film; (f) a second insulating film formed over said first plate electrode; (g) a charge storage electrode formed over said second insulating film and having a part extending through a first contact hole, said first contact hole being provided through said first insulating film, said first plate electrode and said second insulating film, and said part extending through said first contact hole being arranged so as to contact said second diffusion region; (h) a third insulating film formed over said charge storage electrode; and (i) a second plate electrode formed over said third insulating film and having a part extending through a second contact hole, said second contact hole being provided through said second insulating film and said third insulating film, and said part extending through said second contact hole being arranged so as to contact said first plate electrode.
Claim 2
Dependent Claim
208 words
A semiconductor memory integrated circuit device having a stacked capacitor cell comprising: (a) a semiconductor substrate; (b) a first diffusion region, a channel region and a second diffusion region formed in the substrate; (c) a gate insulating film and a gate electrode formed over the channel region; (d) a first insulating film formed over said second diffusion region; (e) a first plate electrode formed over said first insulating film; (f) a second insulating film formed over said first plate electrode; (g) a charge storage electrode formed over said second insulating film and having a part extending through a first contact hole, said first contact hole being provided through said first insulating film, said first plate electrode and said second insulating film, and said part extending through said first contact hole being arranged so as to contact said second diffusion region; (h) a third insulating film formed over said charge storage electrode; and (i) a second plate electrode formed over said third insulating film and having a part extending through a second contact hole, said second contact hole being provided through said second insulating film and said third insulating film, and said part extending through said second contact hole being arranged so as to contact said first plate electrode.
Claim 3
Dependent Claim
54 words
A device according to claim 1, wherein said first and second plate electrodes have a part positioned outside of the periphery of said charge storage electrode and confronting each other, and said second contact hole is provided at said part of said first and second plate electrodes positioned outside of said charge storage electrode.
Claim 4
Dependent Claim
18 words
A device according to claim 1, wherein said second contact hole is formed over an isolation oxide film.
Claim 5
Dependent Claim
45 words
A device according to claim 1, wherein said device comprises a cell area in which a plurality of memory cells are arranged in an array, and a peripheral area outside of said cell area; and said second contact hole is disposed in the peripheral area.
Claim 6
Dependent Claim
29 words
A device according to claim 1, further comprising a fourth insulating film formed on a part of said first plate electrode that is exposed inside said first contact hole.
Claim 7
Dependent Claim
17 words
A device according to claim 1, further comprising a conductor having contact with said first diffusion region.
Claim 8
Dependent Claim
42 words
A device according to claim 1, wherein said first insulating film also extends over said gate electrode, and wherein said first plate electrode, said charge storage electrode and said second plate electrode extend over said second diffusion region and said gate electrode.
Claim 9
Dependent Claim
53 words
A device according to claim 6, wherein said first insulating film extends over the entire cell except where the conductor is in contact with said first diffusion region, and wherein said first plate electrode, said charge storage electrode and said second plate electrode extend over said second diffusion region and said gate electrode.
Claim 10
Dependent Claim
272 words
A semiconductor memory integrated circuit device comprising: a semiconductor substrate; a cell area in which a plurality of memory cells are arranged in an array; and a peripheral area outside of said cell area; each memory cell being in the form of stacked memory cell and comprising: a first diffusion region, a channel region and a second diffusion region formed in the substrate; a gate insulating film and a gate electrode formed over the channel region; a first insulating film formed over said second diffusion, said gate electrode, said first diffusion region, and an isolation oxide region; a first plate electrode formed over said first insulating film and extending to cover said second diffusion, said gate electrode, said first diffusion region, and an isolation oxide region; a second insulating film formed over said first plate electrode; a charge storage electrode formed over said second insulating film and having a part extending through a first contact hole, said first contact hole being provided through said first insulating film, said first plate electrode and said second insulating film, and said part extending through said first contact hole being arranged so as to contact said second diffusion region; a third insulating film formed over said charge storage electrode; and a second plate electrode formed over said third insulating film and having a part extending through a second contact hole, said second contact hole being provided through said second insulating film and said third insulating film, and said part extending through said second contact hole being arranged so as to contact said first plate electrode; wherein said second contact hole is disposed in the peripheral area.
Claim 11
Dependent Claim
272 words
A semiconductor memory integrated circuit device comprising: a semiconductor substrate; a cell area in which a plurality of memory cells are arranged in an array; and a peripheral area outside of said cell area; each memory cell being in the form of stacked memory cell and comprising: a first diffusion region, a channel region and a second diffusion region formed in the substrate; a gate insulating film and a gate electrode formed over the channel region; a first insulating film formed over said second diffusion, said gate electrode, said first diffusion region, and an isolation oxide region; a first plate electrode formed over said first insulating film and extending to cover said second diffusion, said gate electrode, said first diffusion region, and an isolation oxide region; a second insulating film formed over said first plate electrode; a charge storage electrode formed over said second insulating film and having a part extending through a first contact hole, said first contact hole being provided through said first insulating film, said first plate electrode and said second insulating film, and said part extending through said first contact hole being arranged so as to contact said second diffusion region; a third insulating film formed over said charge storage electrode; and a second plate electrode formed over said third insulating film and having a part extending through a second contact hole, said second contact hole being provided through said second insulating film and said third insulating film, and said part extending through said second contact hole being arranged so as to contact said first plate electrode; wherein said second contact hole is disposed in the peripheral area.
Claim 12
Dependent Claim
26 words
A device according to claim 15, wherein said first and second plate electrodes extend throughout the array of memory cells except over the first diffusion region.
Claim 13
Dependent Claim
17 words
A device according to claim 15, wherein said second contact hole is formedover an isolation oxide film.
Claim 14
Dependent Claim
29 words
A device according to claim 9, further comprising a fourth insulating film formed on a part of said first plate electrode that is exposed inside said first contact hole.
Claim 15
Dependent Claim
17 words
A device according to claim 9, further comprising a conductor having contact with said first diffusion region.
Claim 16
Dependent Claim
32 words
A device according to claim 13, wherein said first and second plate electrodes extend throughout the array of memory cells except where said conductor is in contact with said first diffusion region.
References Cited (Backward Citations)
US4700457A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |