CMOS amplifier for memories

Claim 1

A read amplifier for a memory using CMOS technology, said amplifier comprising a differential amplifier having two inputs and two differential branches connected in parallel between a current source and a supply voltage, said amplifier further comprising an output for providing a voltage corresponding to one of a first and second logic level, and a balancing circuit controlled by a precharge signal, said balancing circuit comprising means for short-circuiting the two inputs of the differential amplifier during a balancing phase, wherein there is further provided means controlled by said precharge signal for establishing on the output of said differential amplifier during said balancing phase either a voltage substantially corresponding to a high logic level if the voltage on said output prior to the balancing phase was at a high logic level, or a voltage substantially corresponding to a low logic level if the voltage on said output prior to said balancing phase was at a low logic level.