Bipolar transistor logic circuit

Claim 1

A bipolar transistor logic circuit comprising: an input node; an output node; a first potential node connected to a first potential; a second potential node connected to a second potential, different from said first potential; first transistor circuitry connected to said input node and to said first potential node, wherein said first transistor circuitry comprises a first transistor having its base connected to said input node and a first terminal connected to said first potential node; second transistor circuitry provided between said output node and said first potential node, and further connected to said first transistor circuitry, wherein said second transistor circuitry comprises Darlington-connected transistors, a base of one of said Darlington-connected transistors being connected to said first terminal of said first transistor, first terminals of said Darlington-connected transistors being connected to said first potential node, and a second terminal of the other of said Darlington-connected transistors being connected to said output node; third transistor circuitry connected between said output node and said second potential node, and further connected to said first transistor circuitry, wherein said third transistor circuitry comprises a second transistor having its base connected to a second terminal of said first transistor, a first terminal of said second transistor being connected to said output node, and a second terminal of said second transistor being connected to said second potential node; and accelerated discharge means for discharging charge, stored in a charge storage device that is connected to said output node, to said third transistor circuitry through said first transistor circuitry, said charge being discharged at a time that is delayed with respect to a timing of a change in said first transistor circuitry from a non-conductive state to a conductive state, wherein said accelerated discharge means comprises: switching means connected between said output node and said first terminal of said first transistor, wherein said switching means comprises a third transistor and a diode, a first terminal of said third transistor being connected to a cathode of said diode, an anode of said diode being connected to said output node, a second terminal of said third transistor being connected to said first terminal of said first transistor; and switching delay means, responsive to a change in said first transistor from a non-conductive state to a conductive state, for delaying a corresponding change in conductivity of said switching means from a non-conductive state to a conductive state with respect to a timing of corresponding change in conductivity of said first transistor, wherein said switching delay means comprises: a fourth transistor having a base and first and second terminals, the second terminal of said fourth transistor being connected to a base of said third transistor; and first and second load elements each having one end connected to said first potential node, the other end of said second load element being connected to the first terminal of said fourth transistor.