High-speed schottky TTL gate apparatus

Claim 1

A transistor logic circuit having an input terminal and an output terminal, including a phase splitter transistor, a pulldown circuit, and a pullup circuit; the phase splitter transistor having a base terminal coupled to the input terminal of the logic circuit, an emitter terminal coupled to a reference potential, and a collector terminal coupled to a source of potential, the pulldown circuit being coupled between the output terminal of the logic circuit and the reference potential, the pulldown circuit having an input connected to the emitter terminal of the phase splitter transistor; the pullup circuit including first and second transistor, each having emitter, base, and collector terminals and forming a Darlington output stage, the bse of the first transistor being connected to the collector terminal of the phase splitter transistor, the emitter terminal of the second transistor beig connected to the output terminal of the logic circuit, the emitter terminal of the first transistor being connected to the base terminal of the second transistor, the collector terminals of the first and second transistors being coupled to a source of potential, the improvement comprising: a transistor means for speeding up the switching characteristics of said logic circuit, said transistor means having a collector terminal coupled to said output terminal, an emitter terminal coupled to the collector terminal of said phase splitter transistor, and a base terminal coupled to base terminal of the second transistor of said pullup circuit.