Patent US3334271A successfully refreshed from Google Patents.
Patent US4896155A successfully refreshed from Google Patents.
US4896155A
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Method and apparatus for self-calibration of subranging A/D converter
Assignee: Boeing North American Inc
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Filing: 1988-06-22
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Granted: 1990-01-23
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Expires: 2008-06-22
Abstract
Abstract A subranging analog-to-digital (A/D) converter is provided with a calibration mode for linearity correction. In the calibration mode, an up/down calibration counter provides a digital input to a calibration logic circuit and to an estimator digital-to-analog (D/A) converter. The analog output of the estimator D/A converter is provided as an inverted input to a residue operational amplifier, and is combined with a dither noise signal for input to a sample-and-hold circuit. The output of the sample-and-hold circuit is provided to a noninverting input of the residue operational amplifier. The operational amplifier provides an analog residue signal to a residue A/D converter that generates a digital residue signal for input to the calibration logic circuit. The calibration logic circuit calculates and stores a linearity correction table based on the average step size computed from the inputs to the calibration logic circuit for each step of the up/down counter. The stored correction table is used to provide linearity correction for the subranging A/D converter when it is operating in the run mode.
Inventors
- 👤 Robert L. Craiglow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:44
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1038; H03M1/12; H03M1/14; H03M1/16; H03M1/164; H03M1/167
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
51 words
Apparatus for calibrating a subranging analog-to-digital converter, comprising: means for providing an incrementable calibration signal to the means for incrementing said calibration signal in steps; and means for computing and storing a calibration table based on an average step size generated by the converter for each of said calibration signal steps.
Claim 2
Dependent Claim
51 words
Apparatus for calibrating a subranging analog-to-digital converter, comprising: means for providing an incrementable calibration signal to the means for incrementing said calibration signal in steps; and means for computing and storing a calibration table based on an average step size generated by the converter for each of said calibration signal steps.
Claim 3
Dependent Claim
28 words
The apparatus of claim 1, wherein said means for providing a calibration signal includes a means for switching the converter from a run mode to a calibration mode.
Claim 4
Dependent Claim
25 words
The apparatus of claim 2, wherein said means for providing said calibration signal further comprises means for adding a noise signal to said calibration signal.
Claim 5
Dependent Claim
50 words
The apparatus of claim 2, wherein said means for computing and storing comprises a calibration and correction logic circuit that calculates and stores said calibration table when in said calibration mode and that provides a corrected digital output corresponding to an analog input to the converter in said run mode.
Claim 6
Dependent Claim
41 words
The apparatus of claim 1, wherein said means for incrementing said calibration signal includes means for stepping said calibration signal both up and down in a calibration cycle comprising a multiplicity of calibration trials for each of said calibration signal steps.
Claim 7
Dependent Claim
167 words
Self-calibration apparatus for a subranging analog-to-digital (A/D) converter having an estimator A/D converter and a residue A/D converter, comprising: means for switching between a run mode and a calibration mode, said switching means providing an analog input to a residue operational amplifier and to the estimator A/D converter; a calibration counter for generating digital calibration signals in incremental steps; a data selector for selectively transferring, to an estimator digital-to-analog (D/A) converter and a calibration logic circuit, an output of the estimator A/D converter in said run mode and said calibration signal in said calibration mode; said residue operational amplifier receiving a signal from said estimator D/A converter as a second analog input; the residue A/D converter receiving an output from said residue operational amplifier and providing an input to said calibration logic circuit; said calibration logic circuit computing and storing a calibration table of correction factors for each of said calibration signal steps in said calibration mode and providing a corrected digital output in said run mode.
Claim 8
Dependent Claim
167 words
Self-calibration apparatus for a subranging analog-to-digital (A/D) converter having an estimator A/D converter and a residue A/D converter, comprising: means for switching between a run mode and a calibration mode, said switching means providing an analog input to a residue operational amplifier and to the estimator A/D converter; a calibration counter for generating digital calibration signals in incremental steps; a data selector for selectively transferring, to an estimator digital-to-analog (D/A) converter and a calibration logic circuit, an output of the estimator A/D converter in said run mode and said calibration signal in said calibration mode; said residue operational amplifier receiving a signal from said estimator D/A converter as a second analog input; the residue A/D converter receiving an output from said residue operational amplifier and providing an input to said calibration logic circuit; said calibration logic circuit computing and storing a calibration table of correction factors for each of said calibration signal steps in said calibration mode and providing a corrected digital output in said run mode.
Claim 9
Dependent Claim
34 words
The apparatus of claim 6, further comprising means for stepping said calibration signal both up and down in a calibration cycle comprising a multiplicity of calibration trials for each of said calibration signal steps.
Claim 10
Dependent Claim
35 words
The apparatus of claim 6, further comprising a dither circuit for adding a noise signal to the output of said estimator D/A converter to provide an input to said switching means in said calibration mode.
Claim 11
Independent Claim
45 words
A method of calibrating a subranging analog-to-digital converter, comprising the steps of: providing an incrementable calibration signal to the converter; incrementing said calibration signal in digital steps; and computing and storing a step size generated by the converter for each of said calibration signal steps.
Claim 12
Independent Claim
45 words
A method of calibrating a subranging analog-to-digital converter, comprising the steps of: providing an incrementable calibration signal to the converter; incrementing said calibration signal in digital steps; and computing and storing a step size generated by the converter for each of said calibration signal steps.
Claim 13
Dependent Claim
38 words
The method of claim 9, wherein the step of incrementing said calibration signal includes stepping said calibration signal both up and down in a calibration cycle comprising a multiplicity of calibration trials for each of said calibration steps.
Claim 14
Dependent Claim
48 words
The method of claim 9, wherein the step of providing a calibration signal to the converter further comprises the steps of: converting said calibration signal to an analog signal; and adding a noise signal to said analog signal before the step of computing and storing said step size.
Claim 15
Dependent Claim
57 words
The method of claim 9, further comprising the steps of: storing a calibration table of correction factors derived from said step sizes; switching the converter to a run mode for receiving an analog generating a digital signal corresponding to said analog input; and applying said correction factors to said digital signal to produce a corrected digital output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-22 | 1993-07-24 | 1994-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-22 | 1997-07-24 | 1998-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-22 | 2001-07-24 | 2002-01-23 | $7700.00 | Window Closed / Lapsed |