Signal conditioner for capacitive transducer

Claim 2

Signal conditioning apparatus for operation of a capacitive transducer, comprising: a digital waveform generator for generating a waveform that approximates a sine wave and for generating a binary signal synchronized to said waveform, said waveform having more than two voltage levels; filter means responsive to said waveform for providing a first sinusoidal excitation signal; inverting means responsive to said first sinusoidal excitation signal for providing a second sinusoidal excitation signal that is 180° out of phase with said first excitation signal; means for applying said first and second excitation signals to said transducer so as to produce an output signal from said transducer; and demodulating means responsive to said binary signal for synchronously detecting the output signal from said transducer.

Claim 3

Signal conditioning apparatus as defined in claim 1 wherein said digital waveform generator includes: a clock for generating a clock signal; a multiple-stage shift register responsive to said clock signal, each shift register stage having an output; a resistor network comprising multiple resistors, each having a first terminal connected to one of the output stages of said shift register and having a second terminal connected to a summing point; and means for alternately loading a logic one and a logic zero into said shift register after each half cycle of said waveform, whereby said waveform that approximates a sine wave is produced at said summing point.

Claim 4

Signal conditioning apparatus as defined in claim 2 wherein said shift register is biased to produce at each stage binary output levels of equal voltage and opposite polarity.

Claim 5

Signal conditioning apparatus as defined in claim 3 wherein said shift register comprises a CMOS shift register.

Claim 6

Signal conditioning apparatus as defined in claim 2 wherein said clock comprises a quartz crystal oscillator.

Claim 7

Signal conditioning apparatus as defined in claim 3 wherein said demodulating means comprises an analog single-pole, double-throw switch including first and second analog inputs and a control input responsive to said binary signal, means for applying the output signal of the capacitive transducer to the first analog input of said analog switch, and inverting means responsive to the output signal of the capacitive strain gage for providing an inverted output signal to the second analog input of said analog switch.

Claim 8

Signal conditioning apparatus as defined in claim 5 wherein said analog switch comprises a CMOS analog switch.

Claim 9

A measuring system comprising: a differential capacitive transducer including first and second capacitors connected as a capacitive half-bridge, said first and second capacitors having first and second excitation plates and a common output plate; a digital waveform generator for generating a waveform that approximates a sine wave and for generating a binary signal synchronized to said waveform, said waveform having more than two voltage levels; first filter means responsive to said waveform for providing a first sinusoidal excitation signal coupled to aid first excitation plate; inverting means responsive to said first sinusoidal excitation signal for providing a second sinusoidal excitation signal that is 180° out of phase with said first excitation signal and coupled to said second excitation plate; demodulating means responsive to said binary signal for synchronously detecting a signal on the common output plate of said differential capacitive transducer; and second filter means for removing ana.c. *. component from an output of said demodulating means and providing an output signal.

Claim 10

A measuring system comprising: a differential capacitive transducer including first and second capacitors connected as a capacitive half-bridge, said first and second capacitors having first and second excitation plates and a common output plate; a digital waveform generator for generating a waveform that approximates a sine wave and for generating a binary signal synchronized to said waveform, said waveform having more than two voltage levels; first filter means responsive to said waveform for providing a first sinusoidal excitation signal coupled to aid first excitation plate; inverting means responsive to said first sinusoidal excitation signal for providing a second sinusoidal excitation signal that is 180° out of phase with said first excitation signal and coupled to said second excitation plate; demodulating means responsive to said binary signal for synchronously detecting a signal on the common output plate of said differential capacitive transducer; and second filter means for removing ana.c. *. component from an output of said demodulating means and providing an output signal.

Claim 11

A measuring system as defined in claim 8 wherein said digital waveform generator includes: a clock for generating a clock signal a multiple-stage shift register responsive to said clock signal, each shift register stage having an output; a resistor network comprising multiple resistors, each having a first terminal connected to one of the output stages of having a first terminal connected to one of the output stages of said shift register and having a second terminal connected to a summing point; and means for alternately loading a logic one and a logic zero into said shift register after each half cycle of said waveform, whereby said waveform that approximates a sine wave is produced at said summing point.

Claim 12

A measuring system as defined in claim 9 wherein said shift register is biased to produce at each stage binary output levels of equal voltage and opposite polarity.

Claim 13

A measuring system as defined in claim 10 wherein said shift register comprises a CMOS shift register.

Claim 14

A measuring system as defined in claim 9 wherein said clock comprises a quartz crystal oscillator.

Claim 15

A measuring system as defined in claim 10 wherein said demodulating means comprises: an analog single-pole, double-throw switch including first and second analog inputs and a control input responsive to said binary signal, means for applying the output signal of the capacitive transducer to the first analog input of said analog switch, and inverting means responsive to the output signal of the capacitive strain gage for providing an inverted output signal to the second analog input of said analog switch.

Claim 16

A measuring system as defined in claim 12 wherein said analog switch comprises a CMOS analog switch.