Capacitive circuit for measuring a parameter having a linear output voltage

Claim 2

A capacitive electrical circuit for measuring a parameter, comprising: timing circuitry for providing first, second and third clock signals, and for providing a periodic square wave signal; a capacitive integrating circuit having an integrator, discharge circuitry, a reference capacitor and a sensing capacitor responsive to the external parameter, one of said capacitors responsive to said square wave signal and the other to its inverse, said square wave signal providing alternative charging and discharging of said reference capacitor and said sensing capacitor, said reference and sensing capacitors providing a charge difference signal indicative of the difference in magnitude of the charge stored therein, said integrator responsive to a reference signal and to said charge difference signal for integrating said charge difference signal and providing an integrated output signal indicative of the magnitude of said charge difference, said discharge circuitry discharging said integrator each half cycle of said square wave signal in response to said first clock signal; sampling circuit means including first and second sampling means for alternatively sampling, in alternate half cycles of said square wave signal, said integrated output signal from said capacitive integrating circuit in response to said second and third clock signals, respectively, and providing first and second sampled signals; and a differential amplifier, responsive to said reference signal, and responsive to said first and second sampled signals, for providing from the difference in magnitudes therebetween, a linear signal having a magnitude proportional to the magnitude of the capacitance of said parameter responsive sensing capacitor.

Claim 3

The capacitive electrical circuit of claim 1, wherein said parameter sensitive capacitor means comprises a silicon-glass-silicon capacitive pressure transducer.

Claim 4

The capacitive electrical circuit of claim 1, wherein said capacitive electrical circuit further comprises compensation means responsive to temperature for adjusting the magnitude of said reference signal provided to said differential amplifier in response to a change in temperature of the measuring circuit.

Claim 5

The capacitive electrical circuit of claim 1, wherein said differential amplifier means includes selector means for comparing signals output therefrom with said reference signal and adjusting said feedback circuitry means in dependence thereon.

Claim 6

The capacitive electrical circuit of claim 1, wherein said parameter sensitive capacitor means comprises a capacitive humidity transducer.

Claim 7

Apparatus, comprising: a reference capacitor and a sensing capacitor having a common output node, each having a separate input node, one responsive to a square wave input signal and the other to its inverse, said capacitors alternately providing at said common output node a stored charge signal having a magnitude indicative of the quantity of charge stored therein; an integrator, responsive to each of said stored charge signals for alternately integrating said stored charge signals during each half cycle of said square wave signal for providing an integrated output signal alternately having a magnitude indicative of the charge stored on each of said capacitors; discharge means, responsive to a first periodic timing signal at a frequency in synchronism with but at twice that of said square wave for discharging said integrator at the end of each half cycle of said square wave signal; dual sampling means, having a first half sampling circuit responsive to a second periodic timing signal and a second half sampling circuit responsive to a third periodic timing signal, said second and third timing signals at a frequency in synchronism with and equal to that of said square wave signal but shifted in time with respect to one another by one half cycle, said first half sampling circuit responsive to said second periodic timing signal and to said integrated output signal during each first half cycle of said square wave for storing a first signal having a magnitude indicative of the magnitude of said integrated signal (indicative of the charge stored in one of said capacitors) and said a second half sampling circuit responsive to said third periodic timing signal and to said integrated output signal during each second half cycle of said square wave for storing a second signal having a magnitude indicative of the magnitude of said integrated signal (indicative of the charge stored in the other of said capacitors); and differential amplifier means, responsive to said first and second stored signals for providing a difference signal having a magnitude indicative of the difference in magnitudes between said first and second stored signals.

Claim 8

Apparatus, comprising: a reference capacitor and a sensing capacitor having a common output node, each having a separate input node, one responsive to a square wave input signal and the other to its inverse, said capacitors alternately providing at said common output node a stored charge signal having a magnitude indicative of the quantity of charge stored therein; an integrator, responsive to each of said stored charge signals for alternately integrating said stored charge signals during each half cycle of said square wave signal for providing an integrated output signal alternately having a magnitude indicative of the charge stored on each of said capacitors; discharge means, responsive to a first periodic timing signal at a frequency in synchronism with but at twice that of said square wave for discharging said integrator at the end of each half cycle of said square wave signal; dual sampling means, having a first half sampling circuit responsive to a second periodic timing signal and a second half sampling circuit responsive to a third periodic timing signal, said second and third timing signals at a frequency in synchronism with and equal to that of said square wave signal but shifted in time with respect to one another by one half cycle, said first half sampling circuit responsive to said second periodic timing signal and to said integrated output signal during each first half cycle of said square wave for storing a first signal having a magnitude indicative of the magnitude of said integrated signal (indicative of the charge stored in one of said capacitors) and said a second half sampling circuit responsive to said third periodic timing signal and to said integrated output signal during each second half cycle of said square wave for storing a second signal having a magnitude indicative of the magnitude of said integrated signal (indicative of the charge stored in the other of said capacitors); and differential amplifier means, responsive to said first and second stored signals for providing a difference signal having a magnitude indicative of the difference in magnitudes between said first and second stored signals.