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US4894768A
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Data processing system with coprocessor
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1987-03-02
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Granted: 1990-01-16
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Expires: 2007-03-02
Abstract
Abstract When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal ( &upbar& C/ ) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the &upbar& C/ signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle. Thus, the signal transfer between memory and coprocessor can be completed within one bus cycle without resort to the provision of duplicate hardware in the coprocessor.
Inventors
- 👤 Kazuhiko Iwasaki
- 👤 Tsuneo Funabashi
- 👤 Ikuya Kawasaki
- 👤 Hideo Inayoshi
- 👤 Atsushi Hasegawa
- 👤 Takao Yaginuma
- 👤 Eiki Kondoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:20
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
174 words
A data processing system comprising: a first processor; a second processor; a memory; an address bus interconnecting said first processor, said second processor and said memory; a data bus interconnecting said first processor, said second processor and said memory; a first signal line interconnecting said first processor and said second processor; wherein said first processor fetches an instruction to be processed by said second processor; wherein a command which corresponds to said instruction is sent to said second processor by said first processor over said data bus, wherein instructions fetched by said first processor include a conditional branch instruction whose branch depends on whether a condition for branch is satisfied in said second processor, wherein within one bus cycle said first processor sends a conditional branch command which corresponds to said conditional branch instruction to said second processor over said data bus, and wherein within said one bus cycle said second processor sends a first signal to said first processor over said first signal line indicative of whether said condition for branch is satisfied.
Claim 2
Dependent Claim
174 words
A data processing system comprising: a first processor; a second processor; a memory; an address bus interconnecting said first processor, said second processor and said memory; a data bus interconnecting said first processor, said second processor and said memory; a first signal line interconnecting said first processor and said second processor; wherein said first processor fetches an instruction to be processed by said second processor; wherein a command which corresponds to said instruction is sent to said second processor by said first processor over said data bus, wherein instructions fetched by said first processor include a conditional branch instruction whose branch depends on whether a condition for branch is satisfied in said second processor, wherein within one bus cycle said first processor sends a conditional branch command which corresponds to said conditional branch instruction to said second processor over said data bus, and wherein within said one bus cycle said second processor sends a first signal to said first processor over said first signal line indicative of whether said condition for branch is satisfied.
Claim 3
Dependent Claim
102 words
A data processing system according to claim 1, further comprising: a second signal line interconnecting said first processor and said second processor; wherein within a next consecutive bus cycle after said one bus cycle said first processor sends an address signal over said address bus to said memory and sends a second signal over said second signal line to said second processor, said second signal indicating that said other bus cycle is for transferring data between said second processor said memory, and wherein data is transferred between said second processor and said memory over said data bus within said other bus cycle.
Claim 4
Dependent Claim
266 words
A microprocessor for use in a data processor system, said data processing system including an address bus connected to said microprocessor, a data bus connected to said microprocessor, a memory connected to said address bus and said data bus, a coprocessor connected to said address bus and said data bus, a first signal line connected to said microprocessor and said coprocessor and a second signal line connected to said microprocessor and said coprocessor, wherein said microprocessor fetches an instruction to be processed by said coprocessor, wherein a command which corresponds to said instruction sent to said coprocessor by said microprocessor over said data bus, wherein instructions fetched by said microprocessor includes a conditional branch instruction whose branch depends on whether a condition for branch is satisfied in said Coprocessor wherein within one bus cycle said microprocessor sends a conditional branch command which corresponds to said conditional branch instruction to said coprocessor over said data bus, and wherein within said bus cycle said coprocessor sends a first signal to said microprocessor over said first signal line, indicative of whether said condition for branch is satisfied, said microprocessor comprising: first means for receiving said first signal from said first signal line; and second means for sending an address signal over said address bus to said memory and for sending a second signal over said second signal line to said coprocessor within another bus cycle, said second signal indicating that said other bus cycle is for transferring data between said coprocessor and said memory, whereby data is transferred between said coprocessor and said memory within said other bus cycle.
Claim 5
Dependent Claim
266 words
A microprocessor for use in a data processor system, said data processing system including an address bus connected to said microprocessor, a data bus connected to said microprocessor, a memory connected to said address bus and said data bus, a coprocessor connected to said address bus and said data bus, a first signal line connected to said microprocessor and said coprocessor and a second signal line connected to said microprocessor and said coprocessor, wherein said microprocessor fetches an instruction to be processed by said coprocessor, wherein a command which corresponds to said instruction sent to said coprocessor by said microprocessor over said data bus, wherein instructions fetched by said microprocessor includes a conditional branch instruction whose branch depends on whether a condition for branch is satisfied in said Coprocessor wherein within one bus cycle said microprocessor sends a conditional branch command which corresponds to said conditional branch instruction to said coprocessor over said data bus, and wherein within said bus cycle said coprocessor sends a first signal to said microprocessor over said first signal line, indicative of whether said condition for branch is satisfied, said microprocessor comprising: first means for receiving said first signal from said first signal line; and second means for sending an address signal over said address bus to said memory and for sending a second signal over said second signal line to said coprocessor within another bus cycle, said second signal indicating that said other bus cycle is for transferring data between said coprocessor and said memory, whereby data is transferred between said coprocessor and said memory within said other bus cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |