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US4891792A
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Static type semiconductor memory with multi-stage sense amplifier
Assignee: Hitachi Ltd
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Filing: 1988-07-06
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Granted: 1990-01-02
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Expires: 2008-07-06
Abstract
Abstract Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
Inventors
- 👤 Shoji Hanamura
- 👤 Masaaki Kubotera
- 👤 Katsuro Sasaki
- 👤 Takao Oono
- 👤 Kiyotsugu Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
391 words
A static type semiconductor memory comprising: (1) a plurality of memory arrays each of which includes a plurality of memory cells, a plurality of complementary data line pairs, a first complementary data bus line pair, first switch connected between said plurality of complementary data line pairs, and first amplifier responding to complementary signals on said first complementary data bus line pair, each of said plurality of complementary data line pairs being connected to a selected group of said plurality of memory cells; (2) a second complementary data bus line pair; (3) a second switch connected between complementary outputs of said first amplifier and said second complementary data bus line pair; (4) a second amplifier responding to complementary signals on said complementary outputs of said first amplifier; (5) a third amplifier generating an output signal in response to complementary outputs for said second amplifier; (6) a first equalizer minimizing a level difference of complementary inputs of said first amplifier in response to a first control signal; (7) a second equalizer minimizing a level difference of complementary inputs of said second amplifier in response to a second control signal; and (8) a third equalizer minimizing a level difference of complementary inputs of said third amplifier in response to a third control signal; wherein an operation of said first amplifier is controlled by a fourth control signal; wherein an operation of said second amplifier is controlled by a fifth control signal; wherein an address signal for accessing a selective one from among said plurality of memory cells is supplied to said static type semiconductor memory, wherein levels of said first, second and third control signals are of such values that level difference minimizing operations of said first, second and third equalizers are executed in response to a change of level of said address signal, and thereafter levels of said first, second and third control signals are of values that said level difference minimizing operations of said first, second and third equalizers are not effective, and wherein levels of said fourth and fifth control signals are of such values that said amplifiers operate in high amplification gain conditions in response to the change of level of said address signal, and thereafter levels of said fourth and fifth control signals are of such values that said first and second amplifiers operate in low power consumption conditions.
Claim 2
Dependent Claim
391 words
A static type semiconductor memory comprising: (1) a plurality of memory arrays each of which includes a plurality of memory cells, a plurality of complementary data line pairs, a first complementary data bus line pair, first switch connected between said plurality of complementary data line pairs, and first amplifier responding to complementary signals on said first complementary data bus line pair, each of said plurality of complementary data line pairs being connected to a selected group of said plurality of memory cells; (2) a second complementary data bus line pair; (3) a second switch connected between complementary outputs of said first amplifier and said second complementary data bus line pair; (4) a second amplifier responding to complementary signals on said complementary outputs of said first amplifier; (5) a third amplifier generating an output signal in response to complementary outputs for said second amplifier; (6) a first equalizer minimizing a level difference of complementary inputs of said first amplifier in response to a first control signal; (7) a second equalizer minimizing a level difference of complementary inputs of said second amplifier in response to a second control signal; and (8) a third equalizer minimizing a level difference of complementary inputs of said third amplifier in response to a third control signal; wherein an operation of said first amplifier is controlled by a fourth control signal; wherein an operation of said second amplifier is controlled by a fifth control signal; wherein an address signal for accessing a selective one from among said plurality of memory cells is supplied to said static type semiconductor memory, wherein levels of said first, second and third control signals are of such values that level difference minimizing operations of said first, second and third equalizers are executed in response to a change of level of said address signal, and thereafter levels of said first, second and third control signals are of values that said level difference minimizing operations of said first, second and third equalizers are not effective, and wherein levels of said fourth and fifth control signals are of such values that said amplifiers operate in high amplification gain conditions in response to the change of level of said address signal, and thereafter levels of said fourth and fifth control signals are of such values that said first and second amplifiers operate in low power consumption conditions.
Claim 3
Dependent Claim
53 words
A static type semiconductor memory according to claim 1, wherein levels of said fourth and fifth control signals are set such that, when said first and second amplifiers operate in the low power consumption conditions, information read out through said first and second amplifiers operating in the high amplification gain conditions is held.
Claim 4
Dependent Claim
50 words
A static type semiconductor memory according to claim 2, wherein, after said level difference minimizing operations of said first, second and third equalizers have been made ineffective, the operating conditions of said first and second amplifiers are switched from said high amplification gain conditions to said low power consumption conditions.
Claim 5
Dependent Claim
199 words
A static type semiconductor memory comprising: (1) a plurality of memory cells; (2) a sense amplifier amplifying information read out from a selected one of said plurality of memory cells; and (3) an output buffer circuit generating an output signal at an output terminal in response to complementary output signals from said sense amplifier, said output buffer circuit having; (a) an inverter whose input responds to one of said complementary output signals; (b) an output transistor whose output current path is connected between said output terminal and a first operating potential point and whose control input responds to the output of said inverter; and (c) a wave change control circuit whose input is connected to said input of said inverter and whose output is connected to said output of said inverter, said wave change control circuit including a P-channe MOSFET having the gate thereof connected to said input of said inverter and the source thereof connected to a second operating potential point and an N-channel MOSFET having the drain thereof connected to the drain of said P-channel MOSFET, the gate thereof connected to said second operating potential point and the source thereof connected to said output of said inverter.
Claim 6
Dependent Claim
199 words
A static type semiconductor memory comprising: (1) a plurality of memory cells; (2) a sense amplifier amplifying information read out from a selected one of said plurality of memory cells; and (3) an output buffer circuit generating an output signal at an output terminal in response to complementary output signals from said sense amplifier, said output buffer circuit having; (a) an inverter whose input responds to one of said complementary output signals; (b) an output transistor whose output current path is connected between said output terminal and a first operating potential point and whose control input responds to the output of said inverter; and (c) a wave change control circuit whose input is connected to said input of said inverter and whose output is connected to said output of said inverter, said wave change control circuit including a P-channe MOSFET having the gate thereof connected to said input of said inverter and the source thereof connected to a second operating potential point and an N-channel MOSFET having the drain thereof connected to the drain of said P-channel MOSFET, the gate thereof connected to said second operating potential point and the source thereof connected to said output of said inverter.
Claim 7
Dependent Claim
26 words
A static type semiconductor memory according to claim 4, wherein said inverter is defined by a CMOS inverter, said output transistor being defined by a MOSFET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-01 | 1993-07-03 | 1994-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-01 | 1997-07-03 | 1998-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-01 | 2001-07-03 | 2002-01-02 | $7700.00 | Window Closed / Lapsed |