US4891645A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital-to-analog converter with on-board unity gain inverting amplifier
Assignee: Analog Devices Inc
•
Filing: 1988-10-04
•
Granted: 1990-01-02
•
Expires: 2008-10-04
Abstract
Abstract The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scaled resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense. The effect on the DAC output of the resistance and temperature coefficient of the switches used in the R-2R ladder and elsewhere in the circuitry is minimized by selecting switches appropriately scaled to provide resistances whose sum effect is to cancel each other out. (Particularly, a FET switch biased permanently on is provided at the input of the unity gain inverting operational amplifier.) Since the DAC is monolithic, the switches have approximately equal temperature coefficients such that the effect of the switches is consistent at all temperatures.
Inventors
- 👤 Stephen R. Lewis
- 👤 Scott A. Lefton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:57
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/089; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1057; H03M1/1061; H03M1/66; H03M1/74; H03M1/78; H03M1/785
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
125 words
A digital-to analog converter comprising: a first inverting operational amplifier having an input coupled to receive a reference voltage and an output; a resistive ladder array for converting digital words to corresponding analog currents, having an input coupled to said first inverting amplifier and an output coupled to a summing junction, said resistive ladder array being of the type that divides a current supplied at its input, in accordance with a digital word, and transmits a first portion of said input current to the output of said resistive ladder array and a second portion to an analog ground connection; a second inverting operational amplifier having an input and an output, the input being coupled to the output of said resistive ladder at said summing junction.
Claim 2
Dependent Claim
125 words
A digital-to analog converter comprising: a first inverting operational amplifier having an input coupled to receive a reference voltage and an output; a resistive ladder array for converting digital words to corresponding analog currents, having an input coupled to said first inverting amplifier and an output coupled to a summing junction, said resistive ladder array being of the type that divides a current supplied at its input, in accordance with a digital word, and transmits a first portion of said input current to the output of said resistive ladder array and a second portion to an analog ground connection; a second inverting operational amplifier having an input and an output, the input being coupled to the output of said resistive ladder at said summing junction.
Claim 3
Dependent Claim
91 words
A digital to-analog converter as set forth in claim 1 wherein said resistive ladder array comprises a plurality of resistive leg portions, each leg corresponding to a bit of said digital word and carrying a portion of said current corresponding to the relative weight of the corresponding bit, each of said legs having switch means controlled by said corresponding bit to provide its current portion to analog ground, if the corresponding bit is in a first state, and to the summing junction, if the corresponding bit is in a second state.
Claim 4
Dependent Claim
136 words
A digital to-analog converter as set forth in claim 2 comprising: a second resistive ladder array having an input coupled to said reference voltage source, said second resistive ladder array having a plurality of successive resistive leg portions, but no more than said first resistive ladder, each leg carrying a portion of current which is twice that of the preceeding leg and each of said legs having a switch means controlled by a digital input bit, to said switch means causing the current in the associated leg to flow to said analog ground, if the corresponding bit is a zero, and to a virtual ground which is separate from the analog ground, if the corresponding bit is a one, said second resistive ladder being switched in parallel with the most significant bits of said digital word.
Claim 5
Dependent Claim
54 words
A digital to-analog converter as set forth in claim 3 further comprising a mode select switch which couples said reference voltage to said summing junction when in a first state and which creates an open circuit when in a second state so as to allow for optional bipolar operation when in the first state.
Claim 6
Dependent Claim
80 words
A digital-to analog converter as set forth in claim 4 further comprising: a plurality of gain select switches for alternately coupling the output of said second inverting operational amplifier to the inverting input of said second inverting amplifier through a plurality of resistances, so as to provide a plurality of possible gain factors for said second amplifier; and a biasing switch between said reference voltage source and said first inverting amplifier, said switch being biased permanently in a closed position.
Claim 7
Dependent Claim
22 words
A digital to-analog converter as set forth in claim 5 wherein said plurality of gain select switches comprises first and second switches.
Claim 8
Dependent Claim
23 words
A digital to analog converter as set forth in claim 6 wherein the mode select, gain select and biasing switches are FET switches.
Claim 9
Dependent Claim
66 words
A digital to analog converter as set forth in claim 7 wherein said mode select switch, biasing switch, ladder switch means and said first and second gain select switches each have a resistance and temperature coefficient relative to the other switches such that the net effect of the resistance and temperature coefficients of the switches on the output of the digital to analog converter is zero.
Claim 10
Dependent Claim
25 words
A digital to-analog converter as set forth in claim 8 wherein said digital-to-analog converter is monolithic whereby all the switches have approximately equal temperature coefficients.
Claim 11
Dependent Claim
25 words
A digital-to-analog converter as set forth in claim 9 the first resistive ladder has three times the number of legs as the second resistive ladder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-01 | 1993-07-03 | 1994-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-01 | 1997-07-03 | 1998-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-01 | 2001-07-03 | 2002-01-02 | $7700.00 | Window Closed / Lapsed |