US4488144A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High linearity digital to analog converter
Assignee: Analogic Corp
•
Filing: 1983-04-01
•
Granted: 1984-12-11
•
Expires: 2003-04-01
Abstract
Abstract A digital-to-analog converter having high linearity about zero utilizes a magnitude/sign input code and comprises in combination a single unipolar digital-to-analog converter, a broad bandwidth, offset compensated amplifier and a circuit which multiplies the output of this amplifier by +1 or -1 depending on the sign code.
Inventors
- 👤 Herbert Wollman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:38
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
166 words
A digital-to-analog converter utilizing a magnitude/sign input code comprising in combination: unipolar means for converting the magnitude portion of the digital input code into a corresponding analog input signal; a broad bandwidth amplifier circuit for developing an amplified analog signal at the output thereof, said broad bandwidth amplifier circuit having two inputs, one of said inputs being permanently coupled to the output of said unipolar converting means, said circuit having means for minimizing any AC signal present at said one input of said broadband amplifier circuit; a chopper-stabilized amplifier coupled to the inputs to said broad bandwidth amplifier circuit, said chopper-stabilized amplifier including means coupled to said one input for developing an error signal by sensing substantially only the DC offset of said broad bandwidth amplifier circuit, said error signal being coupled to the other of said inputs of said broad bandwidth amplifier circuit; and means for multiplying the amplified analog signal by +1 or -1 responsive to the sign bit of the digital input code.
Claim 2
Dependent Claim
166 words
A digital-to-analog converter utilizing a magnitude/sign input code comprising in combination: unipolar means for converting the magnitude portion of the digital input code into a corresponding analog input signal; a broad bandwidth amplifier circuit for developing an amplified analog signal at the output thereof, said broad bandwidth amplifier circuit having two inputs, one of said inputs being permanently coupled to the output of said unipolar converting means, said circuit having means for minimizing any AC signal present at said one input of said broadband amplifier circuit; a chopper-stabilized amplifier coupled to the inputs to said broad bandwidth amplifier circuit, said chopper-stabilized amplifier including means coupled to said one input for developing an error signal by sensing substantially only the DC offset of said broad bandwidth amplifier circuit, said error signal being coupled to the other of said inputs of said broad bandwidth amplifier circuit; and means for multiplying the amplified analog signal by +1 or -1 responsive to the sign bit of the digital input code.
Claim 3
Dependent Claim
161 words
The converter of claim 1 wherein said minimizing means includes a feedback resistor coupled between the output of said broad bandwidth amplifier circuit and said one input thereby to form a summing node; a resistor coupled at one end to said summing node; said chopper-stabilized amplifier including means coupled to the other end of said resistor for chopping, amplifying and demodulating the signal at said summing node and for applying said demodulated signal to the other of said inputs; and an attenuating feedback loop from the output of said broad bandwidth amplifier circuit to the other end of said resistor, said feedback loop having an attenuation equal to the open loop gain of said broad bandwidth amplifier circuit such that the voltage at the other end of said resistor is independent of the signal component at said summing node, whereby only a signal reflecting the offset of said broad bandwidth amplifier circuit is chopped and fed back as an error signal.
Claim 4
Dependent Claim
84 words
The converter of claim 1 wherein said multiplying means includes an operational amplifier having two inputs, an output, and a supply of positive and negative voltage; a feedback resistor between said output and one of said inputs; an input terminal; a resistor connected between said input terminal and said one input of said operational amplifier; and, means for selectively connecting the other of said inputs of said operational amplifier to ground or to said input terminal responsive to the state of said sign bit.
Claim 5
Dependent Claim
14 words
The converter of claim 1 wherein said minimizing means includes a high gain amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |