US4891535A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single supply ECL to CMOS converter
Assignee: Tektronix Inc
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Filing: 1988-12-20
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Granted: 1990-01-02
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Expires: 2008-12-20
Abstract
Abstract An ECL to CMOS converter having a diferential ECL clock input and an ECL data input is provided. A reference voltage is generated by averaging the level shifted differential ECL clock signals using a voltage divider. This reference voltage and the level shifted ECL data input are compared by a CMOS comparator to provide a CMOS data output. The level shifters, comparators, and the voltage divider are integrated in a standard VLSI CMOS process that enables the resultant integrated circuit to operate from a single supply voltage.
Inventors
- 👤 Eric P. Etheridge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
74 words
A single supply ECL to CMOS converter comprising: (a) means for shifting ECL data to produce a shifted output; (b) means for shifting an ECL clock to produce a first output; (c) means for shifting an inverted ECL clock to produce a second output; (d) means for generating a reference output from the first and second outputs; and (e) means for comparing the shifted output with the reference output to produce CMOS output data.
Claim 2
Dependent Claim
74 words
A single supply ECL to CMOS converter comprising: (a) means for shifting ECL data to produce a shifted output; (b) means for shifting an ECL clock to produce a first output; (c) means for shifting an inverted ECL clock to produce a second output; (d) means for generating a reference output from the first and second outputs; and (e) means for comparing the shifted output with the reference output to produce CMOS output data.
Claim 3
Dependent Claim
48 words
A single supply ECL to CMOS converter as in claim 1 wherein the means for generating a reference output comprises first and second resistors having one end coupled together to form the reference output, the other end of each resistor each respectively receiving the first and second outputs.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-01 | 1993-07-03 | 1994-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-01 | 1997-07-03 | 1998-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-01 | 2001-07-03 | 2002-01-02 | $7700.00 | Window Closed / Lapsed |