Reliable recovery of data in encoder/decoder

Claim 3

A method according to claim 1 where said plural-bit words are provided to a decoder and then stored in parallel in an elastic buffer, further including the steps: (d) applying said adjusted synchronizing signal to said decoder; and (e) storing said words in said buffer three said inter-bit periods following application of said signal called for at step (d).

Claim 4

Apparatus for decoding serially-received digital signals from a network, said serially-received signals having a predetermined inter-bit period and having a synchronizing signal aligned with a start-of-packet delimiter; and apparatus comprising; means responsive to said serially received signals for generating a recovered clock signal therefrom and for converting said serially-received signals according to a predetermined code; means responsive to said recovered clock signal and to said converted serial signals for generating therefrom plural-bit parallel words corresponding to said serially-received signals; means responsive to said recovered clock signal and to said plural-bit parallel words and to said serially-received signals for generating a synchronizing signal aligned with a start-of-packet delimiter; means responsive to the synchronizing signal generating means for adjusting the synchronizing signal at the time of detection of a delimiter during a predetermined period; and means responsive to said plural-bit parallel words and to said synchronizing signal for decoding said plural-bit parallel words upon receipt of said synchronizing signal and for generating therefrom signals representing said decoding of said plural-bit words.

Claim 5

Apparatus for decoding serially-received digital signals from a network, said serially-received signals having a predetermined inter-bit period and having a synchronizing signal aligned with a start-of-packet delimiter; and apparatus comprising; means responsive to said serially received signals for generating a recovered clock signal therefrom and for converting said serially-received signals according to a predetermined code; means responsive to said recovered clock signal and to said converted serial signals for generating therefrom plural-bit parallel words corresponding to said serially-received signals; means responsive to said recovered clock signal and to said plural-bit parallel words and to said serially-received signals for generating a synchronizing signal aligned with a start-of-packet delimiter; means responsive to the synchronizing signal generating means for adjusting the synchronizing signal at the time of detection of a delimiter during a predetermined period; and means responsive to said plural-bit parallel words and to said synchronizing signal for decoding said plural-bit parallel words upon receipt of said synchronizing signal and for generating therefrom signals representing said decoding of said plural-bit words.

Claim 6

The apparatus according to claim 3, wherein the decoding and generating also generates a WRITE signal, the adjusting means further including first-in, first-out (FIFO) means responsive to said WRITE signal and said decoded plural-bit words for storing said decoded plural-bit words.

Claim 7

The apparatus according to claim 3 wherein said serially-received signals have a start-of-packet delimiter, said adjusting means includes: LOOKAHEAD means responsive to said plural-bit parallel words and said serially-received signals for detecting said delimited during the inter-bit period next following the most recent occurrence of said synchronizing signal and generating a first detection signal thereupon, and for detecting said delimiter during the inter-bit period following by one inter-bit period the most recent occurrence of said synchronizing signal and generating a second detection signal thereupon; means responsive to said first and second detection signals and to said recovered clock signal for generating said synchronizing signal aligned with said start-of-packet delimiter, said generating means including; in the absence of said first or second detection signals means for delaying by two said inter-bit periods upon reception of said first detection signal, and means for delaying said first or second detection signals by one said inter-bit period upon reception of said second detection signal.