Method and apparatus for measuring the speed of an integrated circuit device

Claim 3

The device of claim 1, further comprising an external clock for generating clock signals at a known rate, said external clock being coupled to a terminal count detector circuit means for measuring said predetermined period of time as a predetermined number of said clock signals, said terminal count detector circuit means in turn being coupled to said control logic means.

Claim 4

The device of claim 1, wherein when said control logic means enables said oscillator means, said control logic means also transmits a signal to said counter means to reset said counter value to zero.

Claim 5

The device as described in claim 1, wherein said oscillator means is substantially surrounded by the electronic circuits.

Claim 6

A speed circuit for measuring the speed at which an integrated circuit chip having located thereon a plurality of electronic circuits operates, said speed circuit comprising: an oscillator disposed on said chip, said oscillator generating an output signal, wherein said oscillator comprises a plurality of inverters and a NOR gate, coupled together to form a ring oscillator, said oscillator being adapted to operate in a standby mode and an operational mode, such that in said standby mode said output signal of said oscillator is fixed at a first level and in said operational mode said output signal of said oscillator continuously varies between said first and a second level; a counter coupled to an output line of said oscillator, for counting a number of oscillations of said output signal when said oscillator is in said operational mode; control logic means coupled to said oscillator and said counter, said control logic means selectively issuing an enable signal to said oscillator so as to place said oscillator in said operational mode and, after a predetermined amount of time, selectively issuing a disable signal to said oscillator so as to place said oscillator in said standby mode; processor means coupled to an output of said counter for reading said number of said oscillations counted by said counter after said control logic means issues said disable signal.

Claim 7

A speed circuit for measuring the speed at which an integrated circuit chip having located thereon a plurality of electronic circuits operates, said speed circuit comprising: an oscillator disposed on said chip, said oscillator generating an output signal, wherein said oscillator comprises a plurality of inverters and a NOR gate, coupled together to form a ring oscillator, said oscillator being adapted to operate in a standby mode and an operational mode, such that in said standby mode said output signal of said oscillator is fixed at a first level and in said operational mode said output signal of said oscillator continuously varies between said first and a second level; a counter coupled to an output line of said oscillator, for counting a number of oscillations of said output signal when said oscillator is in said operational mode; control logic means coupled to said oscillator and said counter, said control logic means selectively issuing an enable signal to said oscillator so as to place said oscillator in said operational mode and, after a predetermined amount of time, selectively issuing a disable signal to said oscillator so as to place said oscillator in said standby mode; processor means coupled to an output of said counter for reading said number of said oscillations counted by said counter after said control logic means issues said disable signal.

Claim 8

The device as described in claim 5, wherein said oscillator comprises first and second invertors, each of said invertors having an input and an output, said NOR gate having two inputs and an output, said output of said first invertor being coupled to said input of said second invertor, said output of said second invertor being coupled to said first input of said NOR gate, said output of said NOR gate being coupled to said input of said first invertor.

Claim 9

The device as described in claim 6, wherein said control logic means is coupled to said second input of said NOR gate and said output of said oscillator is coupled to an input of said counter.

Claim 10

The device of claim 7, wherein said oscillator, said counter, and said control logic means are located adjacent to each other on said chip.

Claim 11

The device as described in claim 7, wherein the value stored in said counter increases when said oscillator changes between said first and second levels.

Claim 12

The device as described by claim 4, further including clock means for generating clock signals at a predetermined frequency, said clock means being coupled to said control processor means.

Claim 13

The device as described in claim 10, further including terminal count detector means coupled to said control logic means and said clock means, said detector means counting a predetermined number of said clock signals defining said predetermined amount of time, and said detector means generating a stop signal after said predetermined number of clock signals are counted.

Claim 14

The device as described in claim 11, wherein said stop signal is transmitted from said detector means to said control logic means, said control logic means then placing said oscillator in said standby mode by issuing said enable signal.

Claim 15

The device as described in claim 7, wherein said enable signal comprises transmitting a binary value of 0 from said control logic means to said second input of said NOR gate.

Claim 16

The device as described in claim 7, wherein said disable signal comprises transmitting a binary value of 1 from said control logic means to said second input of said NOR gate.

Claim 17

The device as described in claim 3, wherein said plurality of inverters and said NOR gate are substantially surrounded by the electronic circuitry.

Claim 20

The method as defined by claim 16, further including the step of generating and sending a READ signal from an external processor to said control logic means to read the value of said counter.