Output circuit for CMOS integrated circuit with pre-buffer to reduce distortion of output signal

Claim 2

An output circuit of a CMOS semiconductor integrated circuit comprising: a plurality of CMOS pre-buffer means for receiving the same input signal and outputting a plurality of output signals with different delay times, each including P- and N-channel MOS transistors, each of the P- and N-channel MOS transistors of at least one of said pre-buffer means being formed differently in that the channel width is relatively narrow and channel length is relatively long to provide said pre-buffer means with a relatively small current driving capacity compared to the remaining pre-buffer means; a plurality of CMOS output buffer means, each respectively connected to a corresponding one of said plurality of pre-buffer means, for receiving the plurality of output signals with different delay times from said pre-buffer means and for outputting the plurality of output signals with a greater current driving capacity than the pre-buffer means; and a signal output terminal commonly connected to the output terminals of said plurality of output buffer means for providing an OUT signal.

Claim 3

An output circuit according to claim 1, wherein said pre-buffer means includes a CMOS inverter.

Claim 4

An output circuit according to claim 1, wherein said pre-buffer means includes a NAND gate.

Claim 5

An output circuit according to claim 1, wherein said pre-buffer means includes a NOR gate.

Claim 6

An output circuit according to claim 1, wherein said pre-buffer means includes a logic circuit.

Claim 7

An output circuit according to claim 1, wherein said output buffer means includes a CMOS inverter.

Claim 8

An output circuit according to claim 1, wherein said signal output terminal includes an output pad.

Claim 9

An output circuit for a CMOS integrated circuit, wherein the CMOS integrated circuit includes an internal circuit that provides an IN signal and includes an output terminal for providing an OUT signal externally from the CMOS integrated circuit, and wherein the output circuit comprises: pre-buffer means for receiving the IN signal and for providing a first output signal having a level that rapidly changes in response to changes in the level of the IN signal and a second output signal having a level that slowly changes in response to changes in the level of the IN signal, wherein the pre-buffer means includes first logic means for providing the first output signal, wherein the first logic means includes at least one transistor, each transistor having a relatively wide and short channel to provide the first logic means with a relatively large current driving capacity to rapidly change the level of the first output signal, and second logic means for providing the second output signal, wherein the second logic means includes at least one transistor, each transistor having a relatively narrow and long channel to provide the second logic means with a relatively small current driving capacity to slowly change the level of the second output signal; input coupling means coupled to the internal circuit and to the pre-buffer means, for providing the IN signal to the first logic means and to the second logic means; and output buffer means coupled to the pre-buffer means and to the output terminal, and having a current driving ability greater than the current driving ability of the pre-buffer means, for receiving the first output signal from the first logic means and the second output signal from the second logic means, and for combining the first and second output signals to provide the OUT signal to the output terminal; wherein changes in the level of the OUT signal are delayed by the slow changes in the level of the second output signal, thereby suppressing distortion of the OUT signal when the level of the IN signal changes.

Claim 10

An output circuit for a CMOS integrated circuit, wherein the CMOS integrated circuit includes an internal circuit that provides an IN signal and includes an output terminal for providing an OUT signal externally from the CMOS integrated circuit, and wherein the output circuit comprises: pre-buffer means for receiving the IN signal and for providing a first output signal having a level that rapidly changes in response to changes in the level of the IN signal and a second output signal having a level that slowly changes in response to changes in the level of the IN signal, wherein the pre-buffer means includes first logic means for providing the first output signal, wherein the first logic means includes at least one transistor, each transistor having a relatively wide and short channel to provide the first logic means with a relatively large current driving capacity to rapidly change the level of the first output signal, and second logic means for providing the second output signal, wherein the second logic means includes at least one transistor, each transistor having a relatively narrow and long channel to provide the second logic means with a relatively small current driving capacity to slowly change the level of the second output signal; input coupling means coupled to the internal circuit and to the pre-buffer means, for providing the IN signal to the first logic means and to the second logic means; and output buffer means coupled to the pre-buffer means and to the output terminal, and having a current driving ability greater than the current driving ability of the pre-buffer means, for receiving the first output signal from the first logic means and the second output signal from the second logic means, and for combining the first and second output signals to provide the OUT signal to the output terminal; wherein changes in the level of the OUT signal are delayed by the slow changes in the level of the second output signal, thereby suppressing distortion of the OUT signal when the level of the IN signal changes.

Claim 11

An output circuit according to claim 8, wherein the first and second logic means are inverters.

Claim 12

An output circuit according to claim 8, wherein the first and second logic means are NAND circuits.

Claim 13

An output circuit according to claim 8, wherein the first and second logic means are NOR circuits.

Claim 14

An output circuit according to claim 8, wherein the first logic means comprises: a P-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a first fixed potential, a second terminal, and a channel coupled between the first and second terminals that is relatively wide and short; and an N-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a second fixed potential, a second terminal coupled to the second terminal of the P-channel MOS transistor, and a channel coupled between the first and second terminals that is relatively wide and short.

Claim 15

An output circuit according to claim 12, wherein the second logic means comprises: a P-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to the first fixed potential, a second terminal, and a channel coupled between the first and second terminals that is relatively narrow and long; and an N-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to the second fixed potential, a second terminal coupled to the second terminal of the P-channel MOS transistor, and a channel coupled between the first and second terminals that is relatively narrow and long.

Claim 16

An output circuit according to claim 8, wherein the second logic means comprises: a P-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a first fixed potential, a second terminal, and a channel coupled between the first and second terminals that is relatively narrow and long; and an N-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a second fixed potential, a second terminal coupled to the second terminal of the P-channel MOS transistor, and a channel coupled between the first and second terminals that is relatively narrow and long.

Claim 17

An output circuit according to claim 14, wherein the output buffer means comprises: first output buffer logic means for receiving the first output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; means coupled to the pre-buffer means and the first output buffer logic means, for providing the first output signal from the first logic means to the gates of the P-channel and N-channel transistors in the first output buffer logic means; second output buffer logic means for receiving the second output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; and means coupled to the pre-buffer means and the second output buffer logic means, for providing the second output signal from the second logic means to the gates of the P-channel and N-channel transistors in the second output buffer logic means.

Claim 18

An output circuit according to claim 13, wherein the output buffer means comprises: first output buffer logic means for receiving the first output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; means coupled to the pre-buffer means and the first output buffer logic means, for providing the first output signal from the first logic means to the gates of the P-channel and N-channel transistors in the first output buffer logic means; second output buffer logic means for receiving the second output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; and means coupled to the pre-buffer means and the second output buffer logic means, for providing the second output signal from the second logic means to the gates of the P-channel and N-channel transistors in the second output buffer logic means.

Claim 19

An output circuit according to claim 12, wherein the output buffer means comprises: first output buffer logic means for receiving the first output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; means coupled to the pre-buffer means and the first output buffer logic means, for providing the first output signal from the first logic means to the gates of the P-channel and N-channel transistors in the first output buffer logic means; second output buffer logic means for receiving the second output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; and means coupled to the pre-buffer means and the second output buffer logic means, for providing the second output signal from the second logic means to the gates of the P-channel and N-channel transistors in the second output buffer logic means.

Claim 20

An output circuit according to claim 8, wherein the output buffer means comprises: first output buffer logic means for receiving the first output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to a first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to a second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; means coupled to the pre-buffer means and the first output buffer logic means, for providing the first output signal from the first logic means to the gates of the P-channel and N-channel transistors in the first output buffer logic means; second output buffer logic means for receiving the second output signal, including a P-channel MOS transistor having a gate, a first terminal coupled to the first fixed potential, and a second terminal, and an N-channel MOS transistor having a gate, a first terminal coupled to the second fixed potential, and a second terminal coupled to the second terminal of the P-channel MOS transistor; and means coupled to the pre-buffer means and the second output buffer logic means, for providing the second output signal from the second logic means to the gates if the P-channel and N-channel transistors in the second output buffer logic means.

Claim 21

An output circuit according to claim 8, wherein the first logic means in the pre-buffer means provides a plurality of first output signals.

Claim 22

An output circuit according to claim 19, wherein the first logic means comprises a plurality of first logic circuits, and each first logic circuit comprises: a P-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a first fixed potential, a second terminal, and a channel coupled between the first and second terminals that is relatively wide and short; and an N-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a second fixed potential, a second terminal coupled to the second terminal of the P-channel MOS transistor, and a channel coupled between the first and second terminals that is relatively wide and short.

Claim 23

An output circuit according to claim 19, wherein the second logic means in the pre-buffer means provides a plurality of second output signals.

Claim 24

An output circuit according to claim 21, wherein the second logic means comprises a plurality of second logic circuits, and each second logic circuit comprises: a P-channel MOS transistor having a gate coupled to the input coupling means a first terminal coupled to a first fixed potential, a second terminal, and a channel coupled between the first and second terminals that is relatively narrow and long; and an N-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a second fixed potential, a second terminal coupled to the second terminal of the P-channel MOS transistor, and a channel coupled between the first and second terminals that is relatively narrow and long.

Claim 25

An output circuit according to claim 8, wherein the second logic means in the pre-buffer means provides a plurality of second output signals.

Claim 26

An output circuit according to claim 22, wherein the second logic means comprises a plurality of second logic circuits, and each second logic circuit comprises: a P-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a first fixed potential, a second terminal, and a channel coupled between the first and second terminals that is relatively narrow and long; and an N-channel MOS transistor having a gate coupled to the input coupling means, a first terminal coupled to a second fixed potential, a second terminal coupled to the second terminal of the P-channel MOS transistor, and a channel coupled between the first and second terminals that is relatively narrow and long.