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US4889817A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing schottky gate field transistor by ion implantation method

Assignee: Oki Electric Industry Co Ltd
•
Filing: 1987-12-11
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Granted: 1989-12-26
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Expires: 2007-12-11
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Abstract

Abstract A method of manufacturing a schottky gate field effect transistor with use of a technique of ion implantation comprises the steps of: (a) selectively implantation an ion into a schottky gate field effect transistor formed in a compound semiconductor substrate and (b) annealing the resultant semiconductor substrate at temperature of from 300 DEG C. to 450 DEG C., whereby threshold voltage and a drain current of the schottky gate field effect transistor can be made prescribed values without deteriorating another characteristics of the transistor.

Inventors

  • 👤 Tadashi Saito
  • 👤 Hiroshi Nakamura
  • 👤 Masanori Tsunotani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:16
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10P30/202; H10P30/206; H10P30/28

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 199 words
A method of manufacturing field effect transistors by an ion-implantation technique comprising the steps of: (a) preparing a plurality of compound semiconductor substrates, forming field effect transistors on each of said semiconductor substrates, each of said field effect transistors having an active layer formed by ion-implanting donor ions into said substrate and annealing the same at a temperature of about 800° C., each of said substrates having a source electrode, a drain electrode and a Schottky barrier gate electrode thereon, said source electrode and drain electrode both containing gold and germanium and making ohmic contact with said active layer; (b) measuring a threshold voltage of said field effect transistors and selecting a substrate in which the threshold voltage of the field effect transistor formed thereon has a value deviating negatively from a predetermined designated voltage; and (c) selectively ion-implanting impurity ions, which damage the substrate by causing crytal defects therein, in an amount of less than 1.0 ×10 11 dose/cm 2 into said selected substrate to form an impurity ion profile such as to have a concentration peak thereof at a location in the substrate deeper than that of a concentration peak of donor ions in said active layer.
Claim 2
Independent Claim 199 words
A method of manufacturing field effect transistors by an ion-implantation technique comprising the steps of: (a) preparing a plurality of compound semiconductor substrates, forming field effect transistors on each of said semiconductor substrates, each of said field effect transistors having an active layer formed by ion-implanting donor ions into said substrate and annealing the same at a temperature of about 800° C., each of said substrates having a source electrode, a drain electrode and a Schottky barrier gate electrode thereon, said source electrode and drain electrode both containing gold and germanium and making ohmic contact with said active layer; (b) measuring a threshold voltage of said field effect transistors and selecting a substrate in which the threshold voltage of the field effect transistor formed thereon has a value deviating negatively from a predetermined designated voltage; and (c) selectively ion-implanting impurity ions, which damage the substrate by causing crytal defects therein, in an amount of less than 1.0 ×10 11 dose/cm 2 into said selected substrate to form an impurity ion profile such as to have a concentration peak thereof at a location in the substrate deeper than that of a concentration peak of donor ions in said active layer.
Claim 3
Dependent Claim 45 words
A method of manufacturing a field effect transistor with use of the technique of ion implantation according to claim 1, wherein said method includes a process of annealing said substrate at temperature of from 300° C. to 450° C. after the implantation of said impurity.
Claim 4
Dependent Claim 31 words
A method of manufacturing a field effect transistor with use of the technique of ion implantation according to claim 1, wherein said impurity is less than 80 in its mass number.
Claim 5
Dependent Claim 25 words
A method of manufacturing a field effect transistor with use of the technique of ion implantation according to claim 3, wherein said impurity is boron.

References Cited (Backward Citations)

JPS56155531A Cited
JPS57188877A Cited
US4559238A Cited
US4602965A Cited
US4717685A Cited
JPS622625A Cited
US4701422A Cited
JPH111373A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-12-25 1993-06-26 1993-12-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-12-25 1997-06-26 1997-12-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-12-25 2001-06-26 2001-12-26 $7700.00 Window Closed / Lapsed

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