US4887071A
Expired / Lapsed
US
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Digital activity loss detector
Assignee: Siemens Transmission Systems Inc
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Filing: 1988-08-18
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Granted: 1989-12-12
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Expires: 2008-08-18
Abstract
Abstract A digital activity detection circuit is provided for monitoring digital input signals such as telecommunications DS1 or DS2 signals, and for generating an alarm when a predetermined input signal loss threshold is reached, such that the input signal loss threshold does not vary with temperature, with component value or with power supply variations. Precise resolution and simplified hardware are achieved in a novel arrangement of counters in the signal activity detector to determine the resolution and signal loss threshold of the detector, all in a digital arrangement without the use of analog devices or retriggerable monostable multivibrators, and in an ASIC fabricable integrated circuit technology such as CMOS.
Inventors
- 👤 Nirmal S. Virdee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
188 words
A digital input signal activity loss detector circuit comprising: monitoring means having said digital input signal and a clock signal coupled thereto for detecting data transitions in said digital input signal at a clock signal rate, and for providing an output signal indicative of the detection of a data transition; divide-by-N circuit means for dividing said clock signal by N and providing an output; divide-by-M circuit means for dividing the output of said divide-by-N circuit by M and providing an output; synchronous latch means having coupled thereto the output of said divide-by-N circuit and the output of said divide-by-M circuit for generating a latch output indicative of a said digital input signal loss; logic means coupling the output of said monitoring means to the divide-by-M circuit means and to the synchronous latch means such that said output of said monitoring means indicative of a transition resets said divide-by-M circuit means and resets said synchronous latch means and when no data transition is indicated for a predetermined signal loss threshold time period, said synchronous latch is set to generate said latch output indicative of said digital input signal loss.
Claim 2
Dependent Claim
188 words
A digital input signal activity loss detector circuit comprising: monitoring means having said digital input signal and a clock signal coupled thereto for detecting data transitions in said digital input signal at a clock signal rate, and for providing an output signal indicative of the detection of a data transition; divide-by-N circuit means for dividing said clock signal by N and providing an output; divide-by-M circuit means for dividing the output of said divide-by-N circuit by M and providing an output; synchronous latch means having coupled thereto the output of said divide-by-N circuit and the output of said divide-by-M circuit for generating a latch output indicative of a said digital input signal loss; logic means coupling the output of said monitoring means to the divide-by-M circuit means and to the synchronous latch means such that said output of said monitoring means indicative of a transition resets said divide-by-M circuit means and resets said synchronous latch means and when no data transition is indicated for a predetermined signal loss threshold time period, said synchronous latch is set to generate said latch output indicative of said digital input signal loss.
Claim 3
Dependent Claim
55 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said threshold time period is derived from the output of said divide-by-M circuit and a resolution of said transition detecting is determined by the divide-by-N circuit such that said threshold is: Threshold=N (M+1/2)±N/2 clock pulses where N and M are integers.
Claim 4
Dependent Claim
17 words
A digital input signal activity loss detector circuit in accordance with claim 2 wherein M=3 and N=50.
Claim 5
Dependent Claim
28 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said divide-by-M and divide-by-N circuits include counter means for dividing down said input clock.
Claim 6
Dependent Claim
24 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said synchronous latch includes a NAND gate and a flip-flop.
Claim 7
Dependent Claim
31 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said latch output indicative of said digital input signal loss is coupled to telecommunications alarm indicating equipment.
Claim 8
Dependent Claim
24 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said digital input signal is a DS1 telecommunications transmission signal.
Claim 9
Dependent Claim
24 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said digital input signal is a DS2 telecommunications transmission signal.
Claim 10
Dependent Claim
24 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said circuit is an integrated circuit implemented in CMOS technology.
Claim 11
Dependent Claim
26 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said signal loss threshold time period is substantially invariant with temperature variation.
Claim 12
Dependent Claim
29 words
A digital input signal activity loss detector circuit in accordance with claim 1 wherein said signal loss threshold time period is substantially invariant with variations in power supply voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-11 | 1993-06-12 | 1993-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-11 | 1997-06-12 | 1997-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-11 | 2001-06-12 | 2001-12-12 | $7700.00 | Window Closed / Lapsed |