US4455456A
Expired / Lapsed
US
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Digital supervisory circuit for a telephone system
Assignee: Nokia of America Corp
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Filing: 1982-04-26
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Granted: 1984-06-19
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Expires: 2002-04-26
Abstract
Abstract The digital supervisory circuit comprises an amplitude comparator and EXCLUSIVE-OR gate to provide an output signal indicating the difference in time an input signal is above and below a predetermined reference potential. This output signal is integrated in an up-down binary counter and also is coupled to a first logic circuit under control of the counter which provides a ring present supervisory signal when a first threshold is exceeded and a second logic circuit under control of the counter which provides a switch hook detection supervisory signal when a second threshold is exceeded. A hit-timing circuit is provided coupled to the counter and the first and second logic circuits to prevent response of the counter and second logic circuit to line transients.
Inventors
- 👤 William T. Cochran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:13
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/22; H04M19/00; H04M19/02; H04M19/026
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
160 words
A digital supervisory circuit for a telephone system comprising: first means responsive to an input signal representing at least one of ring trip, ring present, on-hook, off-hook and dial pulses to provide an output signal indicating the difference in time said input signal is above and below a predetermined reference potential; second means coupled to said first means to digitally integrate said output signal; third means coupled to said first means and said second means, said third means having a first predetermined digital threshold to provide a ring present supervisory signal when said first threshold is exceeded; fourth means coupled to said first means and said second means, said fourth means having a second predetermined digital threshold to provide a switch hook detection supervisory signal when said second threshold is exceeded; and fifth means coupled to said second means, said third means and said fourth means to prevent response of said second means and said fourth means to line transients.
Claim 2
Dependent Claim
160 words
A digital supervisory circuit for a telephone system comprising: first means responsive to an input signal representing at least one of ring trip, ring present, on-hook, off-hook and dial pulses to provide an output signal indicating the difference in time said input signal is above and below a predetermined reference potential; second means coupled to said first means to digitally integrate said output signal; third means coupled to said first means and said second means, said third means having a first predetermined digital threshold to provide a ring present supervisory signal when said first threshold is exceeded; fourth means coupled to said first means and said second means, said fourth means having a second predetermined digital threshold to provide a switch hook detection supervisory signal when said second threshold is exceeded; and fifth means coupled to said second means, said third means and said fourth means to prevent response of said second means and said fourth means to line transients.
Claim 3
Dependent Claim
68 words
A circuit according to claim 1, wherein said first means includes an amplitude comparator having a first input for said input signal and a second input for said reference potential, and an EXCLUSIVE-OR gate having one input coupled to the output of said comparator and a second input coupled to a binary signal corresponding to the polarity of said reference potential at said second input of said comparator.
Claim 4
Dependent Claim
14 words
A circuit according to claim 2, wherein said second means includes an integrating counter.
Claim 5
Dependent Claim
15 words
A circuit according to claim 3, wherein said integrating counter includes an up-down binary counter.
Claim 6
Dependent Claim
66 words
A circuit according to claims 3 or 4, wherein said second means further includes sixth means enabling selection of the full scale count of said integrating counter, seventh means coupled to said sixth means to produce a selected clock for said integrating counter, and eighth means coupled to said integrating counter, said fifth means and said seventh means to control the loading of said integrating counter.
Claim 7
Dependent Claim
48 words
A circuit according to claim 5, wherein said third means includes ninth means coupled to said seventh means and said first means to produce said ring present supervisory signal when a predetermined logic condition is present for a predetermined number of consecutive binary ones of said selected clock.
Claim 8
Dependent Claim
14 words
A circuit according to claim 6, wherein said predetermined number is equal to three.
Claim 9
Dependent Claim
14 words
A circuit according to claim 7, wherein said ninth means includes a shift register.
Claim 10
Dependent Claim
60 words
A circuit according to claim 8, wherein said fourth means includes tenth means coupled to said integrating counter to detect one of a plurality of counts of said integrating counter, and eleventh means coupled to said seventh means, said tenth means and said fifth means to provide said switch hook detection supervisory signal when predetermined logic conditions are present therein.
Claim 11
Dependent Claim
52 words
A circuit according to claim 9, wherein said fifth means includes twelfth means coupled to said sixth means to provide a threshold control signal for said eighth means and said fourth means to prevent response thereof to said line transients, said threshold control signal being compatable with said selected full scale count.
Claim 12
Dependent Claim
14 words
A circuit according to claim 1, wherein said second means includes an integrating counter.
Claim 13
Dependent Claim
15 words
A circuit according to claim 11, wherein said integrating counter includes an up-down binary counter.
Claim 14
Dependent Claim
66 words
A circuit according to claims 11 or 12, wherein said second means further includes sixth means enabling selection of the full scale count of said integrating counter, seventh means coupled to said sixth means to produce a selected clock for said integrating counter, and eighth means coupled to said integrating counter, said fifth means and said seventh means to control the loading of said integrating counter.
Claim 15
Dependent Claim
48 words
A circuit according to claim 13, wherein said third means includes ninth means coupled to said seventh means and said first means to produce said ring present supervisory signal when a predetermined logic condition is present for a predetermined number of consecutive binary ones of said selected clock.
Claim 16
Dependent Claim
14 words
A circuit according to claim 14, wherein said predetermined number is equal to three.
Claim 17
Dependent Claim
14 words
A circuit according to claim 15, wherein said ninth means includes a shift register.
Claim 18
Dependent Claim
60 words
A circuit according to claim 16, wherein said fourth means includes tenth means coupled to said integrating counter to detect one of a plurality of counts of said integrating counter, and eleventh means coupled to said seventh means, said tenth means and said fifth means to provide said switch hook detection supervisory signal when predetermined logic conditions are present therein.
Claim 19
Dependent Claim
52 words
A circuit according to claim 17, wherein said fifth means includes twelfth means coupled to said sixth means to provide a threshold control signal for said eighth means and said fourth means to prevent response thereof to said line transients, said threshold control signal being compatible with said selected full scale count.
Claim 20
Dependent Claim
46 words
A circuit according to claim 1, wherein said third means includes sixth means coupled to said first and second means to produce said ring present supervisory signal when a predetermined logic condition is present for a predetermined number of consecutive binary ones of a predetermined clock.
Claim 21
Dependent Claim
14 words
A circuit according to claim 19, wherein said predetermined number is equal to three.
Claim 22
Dependent Claim
14 words
A circuit according to claim 20, wherein said sixth means includes a shift register.
Claim 23
Dependent Claim
63 words
A circuit according to claim 21, wherein said fourth means includes seventh means coupled to an integration counter of said second means to detect one of said plurality of counts of said counter and eighth means coupled to said predetermined clock, said seventh means and said fifth means to provide said switch hook detection supervisory signal when predetermined logic conditions are present therein.
Claim 24
Dependent Claim
44 words
A circuit according to claim 22, wherein said fifth means includes ninth means coupled to a selection means of said second means to provide a threshold control signal for said second means and said fourth means to prevent response thereof to said line transients.
Claim 25
Dependent Claim
63 words
A circuit according to claim 1, wherein said fourth means includes sixth means coupled to an integrating counter of said second means to detect one of a plurality of counts of said counter, and seventh means coupled to a predetermined clock, said sixth means and said fifth means to provide said switch hook detection supervisory signal when predetermined logic conditions are present therein.
Claim 26
Dependent Claim
44 words
A circuit according to claim 24, wherein said fifth means includes eighth means coupled to a selection means of said second means to provide a threshold control signal for said second means and said fourth means to prevent response thereof to said line transients.
Claim 27
Dependent Claim
44 words
A circuit according to claim 1, wherein said fifth means includes sixth means coupled to a selection means of said second means to provide a threshold control signal for said second means and said fourth means to prevent response thereof to said line transients.
Claim 28
Dependent Claim
62 words
A circuit according to claim 1, wherein said first means includes an amplitude comparator, and sixth means coupled to said amplitude comparator to provide a ground potential as said reference potential for said comparator when a call is received by a subscriber and a sine wave signal as said reference potential for said comparator when a call is originated by said subscriber.
Claim 29
Dependent Claim
26 words
A circuit according to claim 1, wherein said first, second, third, fourth and fifth means are at least a portion of a large scale integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-19 | 1987-12-19 | 1988-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-19 | 1991-12-19 | 1992-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-19 | 1995-12-19 | 1996-06-19 | $7700.00 | Window Closed / Lapsed |