Programmable logic array with 2-bit input partitioning

Claim 2

A programmable logic array comprising: input decoding means having a plurality of first transistor means each comprising a pair of transistors connected in series to each other and each first transistor means receiving a different combination of true and complementary input signals, said input decoding means providing logic output signals through respective ones of said first transistor means as a function of said true and complementary input signals applied to said pair of transistors; second transistor means coupled for precharging the input lines of an AND array in accordance with the logic output signals of said input decoding means and a received clock signal; and third transistor means coupled for predischarging the input lines in accordance with the clock signal.

Claim 3

The programmable logic array as claimed in claim 1, wherein said input decoding means comprises inverters receiving the input signals and inverting same to provide the complementary input signals.

Claim 4

A programmable logic array comprising: input decoding means having a plurality of first transistor means each comprising a pair of transistors connected in series to each other and each first transistor means receiving a different combination of true and complementary input signals, said input decoding means providing logic output signals through respective ones of said first transistor means as a function of said true and complementary input signals applied to said pair of transistors; second transistor means coupled for charging up the input lines of an AND array in accordance with the logic output signal of said input decoding means and a received timing control signal; and third transistor means coupled for predischarging the input lines in accordance with the timing control signal.

Claim 5

A programmable logic array comprising: input decoding means having a plurality of first transistor means each comprising a pair of transistors connected in series to each other and each first transistor means receiving a different combination of true and complementary input signals, said input decoding means providing logic output signals through respective ones of said first transistor means as a function of said true and complementary input signals applied to said pair of transistors; second transistor means coupled for charging up the input lines of an AND array in accordance with the logic output signal of said input decoding means and a received timing control signal; and third transistor means coupled for predischarging the input lines in accordance with the timing control signal.

Claim 6

A logic circuit comprising: first and second reference terminals providing first and second reference voltage levels; a decoder composed of a plurality of two bit decoding circuits, each decoding circuit comprising two input terminals for receiving digital input signals and four output terminals, two inverters for providing complementary signals of the digital input signals inputted to said input terminals and four pairs of transistors, each pair having a first and second transistor connected in series to each other between said four output terminals and said first reference voltage level and receiving as the gate signals a different combination of true and complementary digital input signals; a plurality of decoded input lines coupled to the output terminals of said plurality of two bit decoding circuits; a plurality of product term lines each coupled with said first reference voltage level at one end thereof, a plurality of transistors selectively provided to form an AND array, each transistor of said AND array being connected between one of said product term lines and said second reference voltage level with its gate terminal connected to one of said decoded input lines; a first switching means for making or breaking the connections between the output terminals of said plurality of two bit decoding circuit and said decoded input lines in accordance with a timing pulse signal; a second switching means for making or breaking the connection between the second reference voltage level and the other ends of said decoded input line in accordance with said timing pulse signal; and a third switching means for making or breaking the connection between the first reference voltage level and the one ends of said product term lines in accordance with the inverted signal of said timing pulse signal.

Claim 7

A logic circuit comprising: first and second reference terminals providing first and second reference voltage levels; a decoder composed of a plurality of two bit decoding circuits, each decoding circuit comprising two input terminals for receiving digital input signals and four output terminals, two inverters for providing complementary signals of the digital input signals inputted to said input terminals and four pairs of transistors, each pair having a first and second transistor connected in series to each other between said four output terminals and said first reference voltage level and receiving as the gate signals a different combination of true and complementary digital input signals; a plurality of decoded input lines coupled to the output terminals of said plurality of two bit decoding circuits; a plurality of product term lines each coupled with said first reference voltage level at one end thereof, a plurality of transistors selectively provided to form an AND array, each transistor of said AND array being connected between one of said product term lines and said second reference voltage level with its gate terminal connected to one of said decoded input lines; a first switching means for making or breaking the connections between the output terminals of said plurality of two bit decoding circuit and said decoded input lines in accordance with a timing pulse signal; a second switching means for making or breaking the connection between the second reference voltage level and the other ends of said decoded input line in accordance with said timing pulse signal; and a third switching means for making or breaking the connection between the first reference voltage level and the one ends of said product term lines in accordance with the inverted signal of said timing pulse signal.

Claim 8

The circuit of claim 4 wherein said first, second and third switching means comprise transistors receiving the timing pulse signal at gate terminals thereof.

Claim 9

The circuit of claim 4 wherein said timing pulse signal is a clock signal available in a digital system in which said logic circuit is used.

Claim 10

The circuit of claim 4 wherein said first and second reference voltage levels are high and low levels representing the two states of the binary system.