High-speed digital image processing apparatus

Claim 1

A filter circuit for digitally processing video image information of an object to be measured in real time, said video image information being included in an image plane constituted by pixels arranged in a matrix of m-rows and n-columns m and n each being a natural number, based on a pattern of predetermined constants of p-rows and q-columns p and q each being natural numbers, respectively satisfying the condition of p<m and q<n, comprising: time sequenntial output means for time sequentially extracting and outputting pixel data from said image plane; and cascaded filter circuit means connected to said sequential output means for filtering said pixel data, said cascaded filter circuit means comprising a number p of basic filter circuits (100a, 100b, 100c) connected with each other in cascade fashion to form said cascaded filter circuit means, each of said basic filter circuits carrying out an extraction based on said pattern of predetermined constants for the pixel data of one row and q-columns, each of said basic filter circuits comprising first delay means (10) for applying received pixel data to the basic filter circuit of the succeeding stage with a delay of a time corresponding to one row of said image, a number of q-multipliers (20, 21, 22) directly connected in parallel with each other, each multiplier multiplying the received pixel data with a corresponding constannt of said pattern of constants for outputting, and a number of q-sets of adders (30, 31, 32) adn second delay means (40, 41, 42) receiving the output of said adders provided corresponding to each of said multipliers, wherein said q-sets of adders are connected in series with each other, each of said q-adders summing the corresponding multiplier output and the output of the respective basic filter circuit in the preceding stage for outputting the sum to the second delay means in the same set whereby said second delay means receives an output of the adder in the same set and applies a delayed output to the adder in the succeeding set with a delay time corresponding to one column of said image, said filter circuit further comprising means (81) for generating a head indicating bit (I clcp ) indicating the initial bit position of one row of the pixel data from said time sequential output means, and third delay means (50f to 50l, 50m, SW) connected to receive said head indicating bit from said head indictating bit generation means, said third delay means delaying said head indicating bit for a time duration correspondign to a delay time applied to said pixel data.