HgCdTe MIS device having a CdTe heterojunction

Claim 2

A metal-insulated-semiconductor device comprising: a substrate comprised of semiconductor material having a first crystalline structure and further having a first type of electrical conductivity; a layer of passivation overlying at least one surface of said substrate, said passivation layer being comprised of an epitaxial layer of Group II-VI material having a second crystalline structure which is substantially crystallographically continuous and substantially lattice matched with said first crystalline structure, an energy bandgap of said passivation layer being wider than an energy bandgap of said substrate; at least one region having a second type of electrical conductivity disposed within a surface region of said substrate for forming a p-n diode junction, said region having the second type of electrical conductivity being disposed at least partly beneath said passivation layer; a first layer of electrical insulator material overlying said passivation layer; a first plurality of spaced apart gate electrodes disposed upon said first electrical insulator layer; a second layer of electrical insulator material overlying said first layer of electrical insulator material and said first plurality of gate electrodes; and a second plurality of spaced apart gate electrodes disposed upon a top surface of said second electrical insulator layer.

Claim 3

A semiconductor device as defined in claim 1 wherein said substrate is comprised of mercury-cadmium-telluride and wherein said passivation layer comprises cadmium-telluride or cadmium-zinc telluride.

Claim 4

A semiconductor device as defined in claim 1 wherein said substrate is comprised of indium-antimonide and wherein said passivation layer comprises cadmium-telluride or cadmium-zinc-telluride.

Claim 5

A surface mode charge coupled semiconductor device comprising: a substrate comprised of material having a first crystalline structure, said substrate being doped with a first type of inpurity atom for providing said substrate with a first given type of charge carriers; a region formed within a surface of said substrate, said region being doped with a second type of impurity atom for providing said region with a second given type of charge carriers, the interface of said region and said substrate forming a diode junction within said substrate; a passivation layer overlying said surface of said substrate, said passivation layer being comprised of an epitaxial layer of Group II-VI material having a wider energy bandgap than an energy bandgap of said substrate, said passivation layer having a second crystalline structure which is substantially lattice matched with said first crystalline structure; a gate insulator overlying said passivation layer; a channel stop insulator layer overlying said gate insulator layer; a plurality of buried metal gate electrodes disposed in a spaced-apart manner upon a top surface of said channel stop insulator layer; a buried metal insulator layer overlying said channel stop insulator layer and said buried metal gate electrodes; a plurality of surface metal gate electrodes disposed in a spaced-apart manner upon a top surface of said buried metal insulator layer; an input/output diode terminal disposed through each of said layers and being electrically coupled to said region for electrically coupling to said diode; and a channel stop terminal disposed through said buried metal insulator layer and said channel stop insulator, said channel stop terminal being operable for having a voltage potential coupled thereto for terminating a charge carrier conduction channel within said surface of said substrate.

Claim 6

A surface mode charge coupled semiconductor device comprising: a substrate comprised of material having a first crystalline structure, said substrate being doped with a first type of inpurity atom for providing said substrate with a first given type of charge carriers; a region formed within a surface of said substrate, said region being doped with a second type of impurity atom for providing said region with a second given type of charge carriers, the interface of said region and said substrate forming a diode junction within said substrate; a passivation layer overlying said surface of said substrate, said passivation layer being comprised of an epitaxial layer of Group II-VI material having a wider energy bandgap than an energy bandgap of said substrate, said passivation layer having a second crystalline structure which is substantially lattice matched with said first crystalline structure; a gate insulator overlying said passivation layer; a channel stop insulator layer overlying said gate insulator layer; a plurality of buried metal gate electrodes disposed in a spaced-apart manner upon a top surface of said channel stop insulator layer; a buried metal insulator layer overlying said channel stop insulator layer and said buried metal gate electrodes; a plurality of surface metal gate electrodes disposed in a spaced-apart manner upon a top surface of said buried metal insulator layer; an input/output diode terminal disposed through each of said layers and being electrically coupled to said region for electrically coupling to said diode; and a channel stop terminal disposed through said buried metal insulator layer and said channel stop insulator, said channel stop terminal being operable for having a voltage potential coupled thereto for terminating a charge carrier conduction channel within said surface of said substrate.

Claim 7

A semiconductor device as defined in claim 4 wherein said substrate is comprised of mercury-cadmium-telluride and wherein said passivation layer comprises cadmium-telluride or cadmium-zinc-telluride.

Claim 8

A semiconductor device as defined in claim 4 wherein said substrate is comprised of indium-antimonide and wherein said passivation layer comprises cadmium-telluride or cadmium-zinc-telluride.

Claim 9

A semiconductor device as defined in claim 4 wherein said first given type of charge carriers are holes and wherein said second given type of charge carriers are electrons.

Claim 10

The semiconductor device as defined in claim 4 wherein said passivation layer has a thickness of approximately 500 to approximately 1000 angstroms.

Claim 11

A metal-insulator-semiconductor device comprising: a crystalline semiconductor substrate comprised of Group II-VI material and having a first type of electrical conductivity; at least one region disposed within a top surface of said substrate, said region having an opposite type of electrical conductivity for defining a diode junction; a first layer of electrical insulator material disposed over said first substrate, said electrical insulator material layer having a first plurality of gate electrodes disposed upon a top surface of said first layer; a second layer of electrical insulator material overlying said first layer of electrical insulator material and said first plurality of gate electrodes; a second plurality of gate electrodes disposed upon a top surface of said second layer of electrical insulating material; and a passivation layer interposed between said first layer of electrical insulator material and said substrate, said passivation layer being comprised of an epitaxial layer of Group II-VI material which is substantially lattice matched to the Group II-VI material of said substrate, the Group II-VI material of said passivation layer further having a wider energy bandgap than the Group II-VI material of said substrate.

Claim 12

A metal-insulator-semiconductor device comprising: a crystalline semiconductor substrate comprised of Group II-VI material and having a first type of electrical conductivity; at least one region disposed within a top surface of said substrate, said region having an opposite type of electrical conductivity for defining a diode junction; a first layer of electrical insulator material disposed over said first substrate, said electrical insulator material layer having a first plurality of gate electrodes disposed upon a top surface of said first layer; a second layer of electrical insulator material overlying said first layer of electrical insulator material and said first plurality of gate electrodes; a second plurality of gate electrodes disposed upon a top surface of said second layer of electrical insulating material; and a passivation layer interposed between said first layer of electrical insulator material and said substrate, said passivation layer being comprised of an epitaxial layer of Group II-VI material which is substantially lattice matched to the Group II-VI material of said substrate, the Group II-VI material of said passivation layer further having a wider energy bandgap than the Group II-VI material of said substrate.

Claim 13

A semiconductor device as defined in claim 9 wherein said passivation layer has a thickness of approximately 500 to approximately 1000 angstroms.