US4885545A
Expired / Lapsed
US
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High speed circuit with supporting auxiliary circuit
Assignee: Tektronix Inc
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Filing: 1988-08-08
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Granted: 1989-12-05
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Expires: 2008-08-08
Abstract
Abstract A sample-and-hold circuit for sampling a time-varying signal comprises a main sample-and-hold subcircuit extending between input and output terminals and an auxiliary sample-and-hold subcircuit extending between the input terminal and a portion of the main subcircuit. Each sample-and-hold subcircuit comprises an input buffer amplifier, a diode-bridge switch responsive to a control signal and coupled to the input buffer amplifier, a charge-holding capacitor coupled to the switch, and an output buffer amplifier coupled to the capacitor. The output of the auxiliary output amplifier is further coupled to the main switch and the output of the main output amplifier is coupled to the output terminal. A generator generates the control signal for controlling the switches such that the same part of the time-varying signal passing through the main and auxiliary subcircuits is sampled. The time-varying signal passing through the main subcircuit is delayed such that the time-varying signals traveling through the main and auxiliary subcircuits reach the main switch at substantially the same time. The auxiliary subcircuit has a charge-holding capacitor extending between the switch output and ground. The main subcircuit charge-holding capacitor extends between the outputs of the main and axuiliary switch outputs so that the main capacitor only charges to a differential voltage existing between the two switch outputs.
Inventors
- 👤 Sergio A. Sanielevici
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:32
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
200 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main subcircuit coupled between said input and output terminals for conducting the time-varying signal along a first path from said input terminal, through said main subcircuit to said output terminal; an auxiliary subcircuit substantially identical to at least a portion of said main subcircuit and coupled between said input terminal and said main subcircuit for conducting the time-varying signal along a second path from said input terminal, through at least a portion of said auxiliary subcircuit to said main subcircuit; delay means for delaying the time of propagation of the time-varying signal along one of said first and second paths so that the time-varying signal at a selected point along said first path has a predetermined time relationship with respect to the time-varying signal traveling along said second path at the point it is fed to said main subcircuit; and supplemental subcircuit means coupled between said auxiliary subcircuit and said main subcircuit and forming art of said second path for further processing the signal along said second path, said delay means compensating for any propagation delay of the signal passing through said supplemental subcircuit means.
Claim 2
Dependent Claim
200 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main subcircuit coupled between said input and output terminals for conducting the time-varying signal along a first path from said input terminal, through said main subcircuit to said output terminal; an auxiliary subcircuit substantially identical to at least a portion of said main subcircuit and coupled between said input terminal and said main subcircuit for conducting the time-varying signal along a second path from said input terminal, through at least a portion of said auxiliary subcircuit to said main subcircuit; delay means for delaying the time of propagation of the time-varying signal along one of said first and second paths so that the time-varying signal at a selected point along said first path has a predetermined time relationship with respect to the time-varying signal traveling along said second path at the point it is fed to said main subcircuit; and supplemental subcircuit means coupled between said auxiliary subcircuit and said main subcircuit and forming art of said second path for further processing the signal along said second path, said delay means compensating for any propagation delay of the signal passing through said supplemental subcircuit means.
Claim 3
Dependent Claim
154 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main subcircuit coupled between said input and output terminals for conducting the time-varying signal along a first path from said input terminal, through said main subcircuit to said output terminal; an auxiliary subcircuit substantially identical to at least a portion of said main subcircuit and coupled between said input terminal and said main subcircuit for conducting the time-varying signal along a second path from said input terminal, through at least a portion of said auxiliary subcircuit to said main subcircuit; and delay means for delaying the time of propagation of the time-varying signal along one of said first and second paths so that the time-varying signal at a selected point along said first path has no delay with respect to the time varying signal traveling along said second path at the point it is fed to said main subcircuit.
Claim 4
Dependent Claim
154 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main subcircuit coupled between said input and output terminals for conducting the time-varying signal along a first path from said input terminal, through said main subcircuit to said output terminal; an auxiliary subcircuit substantially identical to at least a portion of said main subcircuit and coupled between said input terminal and said main subcircuit for conducting the time-varying signal along a second path from said input terminal, through at least a portion of said auxiliary subcircuit to said main subcircuit; and delay means for delaying the time of propagation of the time-varying signal along one of said first and second paths so that the time-varying signal at a selected point along said first path has no delay with respect to the time varying signal traveling along said second path at the point it is fed to said main subcircuit.
Claim 5
Dependent Claim
188 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main sample-and-hold subcircuit, including a main switch means, a main charge-holding capacitor means and a main output amplifier means, which main subcircuit is coupled between said input and output terminals for conducting the time-varying signal along a first path from said input terminal, through said main subcircuit to said output terminal; an auxiliary sample-and-hold subcircuit, including an auxiliary switch means, an auxiliary charge-holding capacitor means and an auxiliary output amplifier means, which auxiliary subcircuit is coupled between said input terminal and said main switch means for conducting the time-varying signal along a second path from said input terminal, through said auxiliary subcircuit to said main switch means for biasing said main switch means; and delay means for delaying the time of propagation of the time-varying signal along one of said first and second paths so that the time-varying signal at a selected point along said first path has a predetermined time relationship with respect to the time-varying signal traveling along said second path at the point it is fed to said main subcircuit.
Claim 6
Dependent Claim
188 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main sample-and-hold subcircuit, including a main switch means, a main charge-holding capacitor means and a main output amplifier means, which main subcircuit is coupled between said input and output terminals for conducting the time-varying signal along a first path from said input terminal, through said main subcircuit to said output terminal; an auxiliary sample-and-hold subcircuit, including an auxiliary switch means, an auxiliary charge-holding capacitor means and an auxiliary output amplifier means, which auxiliary subcircuit is coupled between said input terminal and said main switch means for conducting the time-varying signal along a second path from said input terminal, through said auxiliary subcircuit to said main switch means for biasing said main switch means; and delay means for delaying the time of propagation of the time-varying signal along one of said first and second paths so that the time-varying signal at a selected point along said first path has a predetermined time relationship with respect to the time-varying signal traveling along said second path at the point it is fed to said main subcircuit.
Claim 7
Dependent Claim
34 words
A circuit according to claim 3 wherein said delay means delays the signal in said first path so that there is substantially no delay between the two signals input to said main switch means.
Claim 8
Dependent Claim
42 words
A circuit according to claim 3 further comprising control signal generating means coupled to said auxiliary and main switch means for generating a control signal appropriate for sampling, respectively, the same point of the time-varying signal along said first and second paths.
Claim 9
Dependent Claim
41 words
A circuit according to claim 5 wherein said control-signal-generating means generates a single control signal and delays the transmission of the control signal to said main switch means relative to the transmission of the control signal to said auxiliary switch means.
Claim 10
Dependent Claim
202 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main subcircuit having a main first portion coupled to said input terminal and a main second portion coupled between said main first portion and said output terminal, said main subcircuit defining a first path of transmission of the time-varying signal; an auxiliary subcircuit having an auxiliary first portion coupled to said input terminal and an auxiliary second portion coupled between said auxiliary first portion and said main first portion, said auxiliary first and second portions being substantially identical to said main first and second portions; delay means for delaying the time of propagation of the time-varying signal from said input terminal along said first path to said main first portion so that the delayed time-varying signal has a predetermined time relationship with respect to the time-varying signal fed along said second path to said main first portion from said auxiliary second portion; and a supplemental subcircuit coupled between said auxiliary subcircuit and said main subcircuit and forming part of said second path for further processing the signal along said second path, said delay means compensating for any propagation delay of the signal passing through said supplemental subcircuit.
Claim 11
Dependent Claim
202 words
A circuit for processing a time-varying signal comprising: an input terminal; an output terminal; a main subcircuit having a main first portion coupled to said input terminal and a main second portion coupled between said main first portion and said output terminal, said main subcircuit defining a first path of transmission of the time-varying signal; an auxiliary subcircuit having an auxiliary first portion coupled to said input terminal and an auxiliary second portion coupled between said auxiliary first portion and said main first portion, said auxiliary first and second portions being substantially identical to said main first and second portions; delay means for delaying the time of propagation of the time-varying signal from said input terminal along said first path to said main first portion so that the delayed time-varying signal has a predetermined time relationship with respect to the time-varying signal fed along said second path to said main first portion from said auxiliary second portion; and a supplemental subcircuit coupled between said auxiliary subcircuit and said main subcircuit and forming part of said second path for further processing the signal along said second path, said delay means compensating for any propagation delay of the signal passing through said supplemental subcircuit.
Claim 12
Dependent Claim
26 words
A circuit according to claim 7 wherein said predetermined time relationship is that there is substantially no delay between the signals at said main first portion.
Claim 13
Dependent Claim
163 words
A sample-and-hold circuit for sampling a time-varying signal comprising: an input terminal; an output terminal; a main sample-and-hold subcircuit and an auxiliary sample-and-hold subcircuit, each sample-and-hold subcircuit comprising an input buffer amplifier coupled to said input terminal, a diode-bridge switch means responsive to a control signal and coupled to said input buffer amplifier, a charge-holding capacitor coupled to said switch means, and an output buffer amplifier coupled to said capacitor; the output of said auxiliary output amplifier further being coupled to said main switch means and the output of said main output amplifier being coupled to said output terminal; control-signal-generating means for generating the signal for controlling said switch means such that the same part of the time-varying signal passing through said main and auxiliary subcircuits is sampled; and delay means for delaying the time-varying signal passing through said main subcircuit such that the time-varying signals traveling through said main and auxiliary subcircuits reach said main switch means at substantially the same time.
Claim 14
Dependent Claim
163 words
A sample-and-hold circuit for sampling a time-varying signal comprising: an input terminal; an output terminal; a main sample-and-hold subcircuit and an auxiliary sample-and-hold subcircuit, each sample-and-hold subcircuit comprising an input buffer amplifier coupled to said input terminal, a diode-bridge switch means responsive to a control signal and coupled to said input buffer amplifier, a charge-holding capacitor coupled to said switch means, and an output buffer amplifier coupled to said capacitor; the output of said auxiliary output amplifier further being coupled to said main switch means and the output of said main output amplifier being coupled to said output terminal; control-signal-generating means for generating the signal for controlling said switch means such that the same part of the time-varying signal passing through said main and auxiliary subcircuits is sampled; and delay means for delaying the time-varying signal passing through said main subcircuit such that the time-varying signals traveling through said main and auxiliary subcircuits reach said main switch means at substantially the same time.
Claim 15
Dependent Claim
52 words
A sample-and-hold circuit according to claim 9 further comprising switch-biasing means posed between said auxiliary output amplifier and said main switch means for biasing said switch means with the signal output from said auxiliary output amplifier, said delay means compensating for any propagation delay of the signal passing through said switch-biasing means.
Claim 16
Dependent Claim
21 words
A sample-and-hold circuit according to claim 9 wherein said delay means delays the time-varying signal before it enters said main subcircuit.
Claim 17
Dependent Claim
69 words
A sample-and-hold circuit according to claim 9 wherein said auxiliary capacitor is coupled for storing the voltage of the time-varying signal received from said auxiliary switch means and said main capacitor is coupled between the outputs of said main and auxiliary switch means for storing the difference in voltage between the voltage of the time-varying signal output from said main switch means and the voltage on said auxiliary capacitor.
Claim 18
Dependent Claim
192 words
A sample-and-hold circuit for sampling a time-varying signal comprising: an input terminal for receiving the time-varying signal; an output terminal; an auxiliary sample-and-hold subcircuit comprising auxiliary switch means responsive to a control signal and coupled to said input terminal, and an auxiliary charge-holding capacitor coupled to said switch means for holding substantially the voltage of the time-varying signal received through said auxiliary switch means, a main sample-and-hold subcircuit comprising main switch means responsive to a control signal and coupled between said input and output terminals, and a main charge-holding capacitor coupled between the outputs of said main and auxiliary switch means for holding substantially the difference in voltage between the voltage of the time-varying signal received through said main switch means and the voltage on said auxiliary capacitor; and control-signal-generating means for generating the signals for controlling said auxiliary and main switch means between a tracking state wherein the input time-varying signal is passed from said input terminal to said auxiliary and main capacitors, and a holding stae wherein the charge existing on said auxiliary and main capacitors is held substantially at the level existing at the beginning of the holding state.
Claim 19
Dependent Claim
192 words
A sample-and-hold circuit for sampling a time-varying signal comprising: an input terminal for receiving the time-varying signal; an output terminal; an auxiliary sample-and-hold subcircuit comprising auxiliary switch means responsive to a control signal and coupled to said input terminal, and an auxiliary charge-holding capacitor coupled to said switch means for holding substantially the voltage of the time-varying signal received through said auxiliary switch means, a main sample-and-hold subcircuit comprising main switch means responsive to a control signal and coupled between said input and output terminals, and a main charge-holding capacitor coupled between the outputs of said main and auxiliary switch means for holding substantially the difference in voltage between the voltage of the time-varying signal received through said main switch means and the voltage on said auxiliary capacitor; and control-signal-generating means for generating the signals for controlling said auxiliary and main switch means between a tracking state wherein the input time-varying signal is passed from said input terminal to said auxiliary and main capacitors, and a holding stae wherein the charge existing on said auxiliary and main capacitors is held substantially at the level existing at the beginning of the holding state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-04 | 1993-06-05 | 1993-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-04 | 1997-06-05 | 1997-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-04 | 2001-06-05 | 2001-12-05 | $7700.00 | Window Closed / Lapsed |