Gated dividing circuit with reduced time variation between gating and an output signal

Claim 2

In a gated dividing circuit which produces, when enabled, an output signal that changes state in response to a predetermined number of unique changes in an input signal applied thereto, the improvement comprising, at least one additional gated dividing circuit substantially identical to the first-mentioned circuit and gated in synchronism therewith, means responsive to said input signal to said first-mentioned circuit for applying delayed versions thereof to said additional circuits, respectively, and means connected to receive the output signals of all of said circuits to produce an output signal in response to a predetermined number of said circuit output signals being in a predetermined state.

Claim 3

A combination in accordance with claim 1 in which the last-mentioned means comprises at least one OR gate having input terminals connected to receive the output signals of all of said circuits.

Claim 4

A combination in accordance with claim 2 in which the last-mentioned means further comprises, a latching circuit connected to receive the output signals of all of said circuits and, in response to the first output signal received, to disable all of said circuits with the exception of the one producing said first output signal.

Claim 5

A combination in accordance with claim 1 in which the last-mentioned means comprises, a plurality of AND gates equal in number to and respectively identifiable with said circuits, means connecting each of said AND gates to receive the output signals of at least two of said circuits none of which are identified with that AND gate, and an OR gate connected to receive the outputs of all of said AND gates.

Claim 6

In an electronic frequency divider comprising a binary circuit which produces an output sIgnal that changes between first and second states in response to a particular change in an input signal thereto, the improvement comprising, at least one additional binary circuit substantially identical to said binary circuit in said divider, means simultaneously enabling said circuits, means for applying delayed versions of said input signal to said additional circuits, respectively, whereby the input signal is applied in an increasing delayed manner to successive ones of said circuits, and means connected to receive the output signals from all of said circuits to produce an output signal in response to a predetermined number of said circuit output signals being in a predetermined one of said states.

Claim 7

In an electronic frequency divider comprising a binary circuit which produces an output sIgnal that changes between first and second states in response to a particular change in an input signal thereto, the improvement comprising, at least one additional binary circuit substantially identical to said binary circuit in said divider, means simultaneously enabling said circuits, means for applying delayed versions of said input signal to said additional circuits, respectively, whereby the input signal is applied in an increasing delayed manner to successive ones of said circuits, and means connected to receive the output signals from all of said circuits to produce an output signal in response to a predetermined number of said circuit output signals being in a predetermined one of said states.

Claim 8

A combination in accordance with claim 5 in which the last-mentioned means comprises at least one OR gate having input terminals connected to receive the output signals of all of said circuits.

Claim 9

A combination in accordance with claim 6 in which the last-mentioned means further comprises, a latching circuit connected to receive the output signals of all of said circuits and, in response to the first output signal received, to disable all of said circuits with the exception of the one producing said first output signal.

Claim 10

A combination in accordance with claim 5 in which the last-mentioned means comprises, a plurality of AND gates equal in number to and respectively identifiable with said circuits, means connecting each of said AND gates to receive the output signals of at least two of said circuits none of which are identified with that AND gate, and an OR gate connected to receive the outputs of all of said AND gates.

Claim 11

In combination, n binary stages where the output of each stage changes between first and second states in response to a particular change in an input signal and n is an integer at least equal to two, an input terminal for receiving a clock pulse train having a predetermined period, means connecting said input terminal to a first of said binary stages, means connecting said input terminal to the remainder of said binary stages to apply delayed versions of said clock pulse train thereto, respectively, wherein the delay increases from stage to stage by an amount substantially equal to said period divided by n, and means connected to said stages to produce an output signal in response to a predetermined number of said stages being in a predetermined one of said states.

Claim 12

In combination, n binary stages where the output of each stage changes between first and second states in response to a particular change in an input signal and n is an integer at least equal to two, an input terminal for receiving a clock pulse train having a predetermined period, means connecting said input terminal to a first of said binary stages, means connecting said input terminal to the remainder of said binary stages to apply delayed versions of said clock pulse train thereto, respectively, wherein the delay increases from stage to stage by an amount substantially equal to said period divided by n, and means connected to said stages to produce an output signal in response to a predetermined number of said stages being in a predetermined one of said states.

Claim 13

A combination in accordance with claim 9 in which the last-mentioned means comprises at least one OR gate having input terminals connected to receive the outputs of all of said stages.

Claim 14

A combination in accordance with claim 10 in which the last-mentioned means further comprises, a latching circuit connected to receive the outputs of all of said stages and, in response to the first output received, to disable all of said stages with the exception of the one producing said first output.

Claim 15

A combination in accordance with claim 9 in which the last-mentioned means comprises, a plurality of AND gates equal in number to and respectively identifiable with said stages, means connecting each of said AND gates to receive the outputs of at least two of said stages none of which are identified with that AND gate, and an OR gate connected to receive the outputs of all of said AND gates.